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型号： XC4VLX15-11FFG676I
厂商： XILINX INC
元件分类： FPGA
英文描述： FPGA, 1536 CLBS, 1205 MHz, PBGA676
封装： LEAD FREE, FBGA-676
文件页数： 52/58页
文件大小： 1863K
代理商： XC4VLX15-11FFG676I
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
56
12/11/06
(Cont’d)
2.0
(Cont’d)
Table 50: Removed T_LOCK_FX_MIN parameter. Added DCM_RESET.
Table 53: Added Note (1), no minimum frequency for PMCD.
Table 64: Added Note (1) to refer to LX and SX Errata for capability improvements.
03/27/07
2.1
SPEED SPECIFICATION version for this data sheet release: v1.64.
Table 4: Added Note (6) regarding max quiescent supply current.
Table 5: Filled in missing power-on current values for FX devices.
Table 24: Added new parameter FGREFCLK. Added Min value for Spread Spectrum
Clocking frequency. Corrected “Conditions”.
Table 26: Revised Notes (2) and (3).
Table 37, Table 38: Added column/values for XC4VFX -12.
Table 39: Added columns/values for XC4VFX -11 and -12. Corrected XC4VLX/SX -11
and -12 values for TREGXB, TREGYB, and TCKSH.
Table 43: Restored parameter TCONFIG and footnote (1) from earlier revision. Added
new parameter TSMCO (SelectMAP Readback Clock-to-Out).
Table 50: Restored DCM_RESET Minimum and DCM_INPUT_CLOCK_STOP
parameters from earlier revision. Added Notes (4) through (7) to these parameters.
Table 60: Removed FF1760 package. Not supported.
Table 63: Added FX devices and JTAG IDs.
06/08/07
2.2
SPEED SPECIFICATION version for this data sheet release: v1.65.
Table 14: Promoted -12 speed grade devices of XC4VFX12, XC4VFX20, and
XC4VFX60 to Production status.
Table 37: Removed parameter TISCCK_REV. Not meaningful because pin should always
be connected to GND.
Table 43: Added parameter FMAX_SELECTMAP. for maximum Slave SelectMAP mode
external configuration clock frequency.
Table 63: Filled in Step 1 values for XC4VFX20, XC4VFX60, and XC4VFX100.
Table 65: Added Step 1 data.
08/10/07
2.3
SPEED SPECIFICATION version for this data sheet release: v1.65.
Table 3: Added MAX value for IBATT .
Table 25: Added unit (ns) to RXSIGDET.
Table 27: Added Note (3) specifying range of DCI reference resistors and referring to
UG070.
Added section Ethernet MAC Switching Characteristics, page 22, and replaced
Table 29.
Added section I/O Standard Adjustment Measurement Methodology, page 23,
including Table 30, Table 31, and Figure 4.
Table 43: Added parameter FMAX_ICAP. Added word “Data” to description of
SelectMAP Setup/Hold.
Table 64: Added to Capability Improvements, for Step 1 that the DFS macro is no
longer needed.
09/10/07
2.4
SPEED SPECIFICATION version for this data sheet release: v1.67.
Table 14: Promoted all speed grades for XC4VFX40 devices, and -12 speed grade for
XC4VFX100 devices, to Production status.
Table 63: Filled in Step 1 value for XC4VFX40.
Table 65: Added Note 1.
Date
Version
Revisions
相关PDF资料
PDF描述
XC4VLX15-12FFG676C FPGA, 1536 CLBS, 1205 MHz, PBGA676
XC4VFX100-10FF1152I FPGA, 10544 CLBS, 1028 MHz, PBGA1152
XC4VFX100-10FF1517I FPGA, 10544 CLBS, 1028 MHz, PBGA1517
XC4VFX100-11FF1152I FPGA, 10544 CLBS, 1181 MHz, PBGA1152
XC4VFX100-11FF1517I FPGA, 10544 CLBS, 1181 MHz, PBGA1517
相关代理商/技术参数
参数描述
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XC4VLX15-11SFG363C 功能描述:IC FPGA VIRTEX-4 LX 15K 363FCBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Virtex®-4 LX 产品变化通告:Step Intro and Pkg Change 11/March/2008 标准包装:1 系列:Virtex®-5 SXT LAB/CLB数:4080 逻辑元件/单元数:52224 RAM 位总计:4866048 输入/输出数:480 门数:- 电源电压:0.95 V ~ 1.05 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:1136-BBGA，FCBGA 供应商设备封装:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
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