- 您现在的位置：买卖IC网 > PDF目录225572 > XC4VLX15-11FFG676I (XILINX INC) FPGA, 1536 CLBS, 1205 MHz, PBGA676 PDF资料下载
参数资料
| 型号： | XC4VLX15-11FFG676I |
| 厂商： | XILINX INC |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1536 CLBS, 1205 MHz, PBGA676 |
| 封装： | LEAD FREE, FBGA-676 |
| 文件页数： | 37/58页 |
| 文件大小： | 1863K |
| 代理商： | XC4VLX15-11FFG676I |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页当前第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
42
Table 50: Miscellaneous Timing Parameters
Symbol
Description
Speed Grade
Units
-12
-11
-10
Time Required to Achieve LOCK
T_LOCK_DLL_240
DLL output – Frequency range > 240 MHz (2)
20
s
T_LOCK_DLL_120_240
DLL output – Frequency range 120 - 240 MHz (1,2)
63
s
T_LOCK_DLL_60_120
DLL output – Frequency range 60 - 120 MHz (1,2)
225
s
T_LOCK_DLL_50_60
DLL output – Frequency range 50 - 60 MHz(1,2)
325
s
T_LOCK_DLL_40_50
DLL output – Frequency range 40 - 50 MHz (1,2)
500
s
T_LOCK_DLL_30_40
DLL output – Frequency range 30 - 40 MHz (1,2)
900
s
T_LOCK_DLL_24_30
DLL output – Frequency range 24 - 30 MHz(1,2)
1250
s
T_LOCK_DLL_30
DLL output – Frequency range < 30 MHz (2)
1250
s
T_LOCK_FX_MAX
DFS outputs(3)
10
ms
T_LOCK_DLL_FINE_SHIFT
Multiplication factor for DLL lock time with Fine Shift
2
Fine Phase Shifting
FINE_SHIFT_RANGE_MS
Absolute shifting range in maximum speed mode
7
ns
FINE_SHIFT_RANGE_MR
Absolute shifting range in maximum range mode
10
ns
Delay Lines
DCM_TAP_MS_MIN
Tap delay resolution (Min) in maximum speed mode
5
ps
DCM_TAP_MS_MAX
Tap delay resolution (Max) in maximum speed mode
40
ps
DCM_TAP_MR_MIN
Tap delay resolution (Min) in maximum range mode
10
ps
DCM_TAP_MR_MAX
Tap delay resolution (Max) in maximum range mode
60
ps
Input Signal Requirements
DCM_RESET(4)
Minimum duration that RST must be held asserted
200
ms
Maximum duration that RST can be held asserted(5)
10
sec
DCM_INPUT_CLOCK_STOP
Maximum duration that CLKIN and CLKFB can be
stopped(6,7)
100
ms
Notes:
1.
For boundary frequencies, choose the higher delay.
2.
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
3.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
4.
CLKIN must be present and stable during the DCM_RESET.
5.
This only applies to production step 1 LX and SX devices. For these devices, use the design solutions described in Answer Record 21127 for support
of longer reset durations. Production step 2 LX and SX devices and all production FX devices do not have this requirement.
6.
For production step 1 LX and SX devices, use the design solutions described in Answer Record 21127 for support of longer durations of stopped
clocks. For production step 2 LX and SX devices and all production FX devices, the ISE software automatically inserts a small macro to support
longer durations of stopped clocks.
7.
For all stepping levels, once the input clock is toggling again and stable after being stopped, DCM must be reset.
相关PDF资料 |
PDF描述 |
|---|---|
| XC4VLX15-12FFG676C | FPGA, 1536 CLBS, 1205 MHz, PBGA676 |
| XC4VFX100-10FF1152I | FPGA, 10544 CLBS, 1028 MHz, PBGA1152 |
| XC4VFX100-10FF1517I | FPGA, 10544 CLBS, 1028 MHz, PBGA1517 |
| XC4VFX100-11FF1152I | FPGA, 10544 CLBS, 1181 MHz, PBGA1152 |
| XC4VFX100-11FF1517I | FPGA, 10544 CLBS, 1181 MHz, PBGA1517 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XC4VLX15-11SF363C | 制造商:Xilinx 功能描述:FPGA VIRTEX-4 13824 CELLS 90NM 1.2V 363FCBGA - Trays |
| XC4VLX15-11SF363I | 功能描述:IC FPGA VIRTEX-4LX 363FCBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Virtex®-4 LX 产品变化通告:Step Intro and Pkg Change 11/March/2008 标准包装:1 系列:Virtex®-5 SXT LAB/CLB数:4080 逻辑元件/单元数:52224 RAM 位总计:4866048 输入/输出数:480 门数:- 电源电压:0.95 V ~ 1.05 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:1136-BBGA，FCBGA 供应商设备封装:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC4VLX15-11SFG363C | 功能描述:IC FPGA VIRTEX-4 LX 15K 363FCBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Virtex®-4 LX 产品变化通告:Step Intro and Pkg Change 11/March/2008 标准包装:1 系列:Virtex®-5 SXT LAB/CLB数:4080 逻辑元件/单元数:52224 RAM 位总计:4866048 输入/输出数:480 门数:- 电源电压:0.95 V ~ 1.05 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:1136-BBGA，FCBGA 供应商设备封装:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC4VLX15-11SFG363I | 功能描述:IC FPGA VIRTEX-4 LX 15K 363FCBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Virtex®-4 LX 产品变化通告:Step Intro and Pkg Change 11/March/2008 标准包装:1 系列:Virtex®-5 SXT LAB/CLB数:4080 逻辑元件/单元数:52224 RAM 位总计:4866048 输入/输出数:480 门数:- 电源电压:0.95 V ~ 1.05 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:1136-BBGA，FCBGA 供应商设备封装:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC4VLX15-12FF668C | 制造商:Xilinx 功能描述:FPGA VIRTEX-4 13824 CELLS 90NM 1.2V 668FCBGA - Trays |
发布紧急采购，3分钟左右您将得到回复。