收藏本站
参数资料
型号： XC4VLX15-11FFG676I
厂商： XILINX INC
元件分类： FPGA
英文描述： FPGA, 1536 CLBS, 1205 MHz, PBGA676
封装： LEAD FREE, FBGA-676
文件页数： 49/58页
文件大小： 1863K
代理商： XC4VLX15-11FFG676I
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
53
Revision History
The following table shows the revision history for this document.
Date
Version
Revisions
08/02/04
1.0
Initial Xilinx release. Printed Handbook version.
09/09/04
1.1
Edits in Tables 12, 13, 18, 19, 20, 22, 26, 28, 37, and 38. Removed Table 39.
01/18/05
1.2
Added parameters to Tables 4 and 5. Removed System Monitor and ADC parameters.
02/01/05
1.3
Changed parameters in Tables 1, 2, 3, 7, and 11. Added Interface Performance
Characteristics section. Added Switching Characteristics section and Table 14. Added
parameters to the following tables: 4–6, 14, 16–30, 32–40, and 46.
02/24/05
1.4
Changed the notes in Table 2. Added Set/Reset parameters to Table 32 and Table 33.
Changed description in Table 35. Changed Set/Reset in Table 37. Changed PSCLK units in
Table 45. Added parameters to Table 46. Changed DCM_TAP_MS_MIN in Table 50.
05/19/05
1.5
Added RocketIO and PowerPC parameters to Table 1, Table 2, and Table 3. Removed
conditions from VIDIFF and VICM in Table 9. Revised Table 13. Added RocketIO DC Input
and Output Levels section. Added PowerPC Switching Characteristics section. Added
RocketIO Switching Characteristics section. Removed Table 31 from version 1.4.
Revised Table 35. Along with changes to Table 43 and Table 50, there are three new
requirements to ensure maximum operating frequencies for the DCM. Added parameters to
Table 54, Table 55, Table 56, Table 58, Table 59, Table 60, Table 61, Table 62.
06/17/05
1.6
Revised VIN and VTS in Table 1 and Note 4. Revised typical PCPU specification in Table 3.
Revised symbols and values in the Processor tables: Table 16 through Table 22. Revised
TDCREF in Table 24. Corrected the CLKOUT_FREQ_FX_HF_MS_MIN in Table 45, the
CLKOUT_FREQ_FX_LF_MR_MIN in Table 46, and the “Input Clock Period Jitter” in
Table 47. Corrected units in Table 59.
06/27/05
1.7
Changed VIL and VIH for LVCMOS15 in Table 7. Revised Table 14. Replaced value for VEYE
in Table 25. Added Note 4 to Table 50. Added Table 57: Global Clock Setup and Hold for
LVCMOS25 Standard, with DCM in Source-Synchronous Mode. Added value for
XC4VLX160-FF1513 in Table 60. Added values for -12 speed specifications to most of the
tables. Revised the -10 and -11 speeds in most of the switching characteristics tables.
08/06/05
1.8
Updated to speed specification v1.56. Added VCC_CONFIG note to Table 2. Clarified design
information in Table 13. Corrected TPROGRAM in Table 43. Added DRP configuration timing
for DCMs to Table 43. Added global clock tree maximum frequency to Table 44. Corrected
CLKOUT_FREQ_FX_LF_MS_MIN in Table 45. Added footnotes 3 and 4 to Table 45 and
Table 46. Added more data to the TCKSKEW in Table 59.
08/29/05
1.9
Corrected VOCM in Table 8. Revised Table 11. Added RocketIO MGT Clock DC Input
Levels to Table 12. Revised SFI-4.1 performance values in Table 13. Added software tools
requirements ISE7.1i SP4, to description above Table 14. Added -11X speed grade to
Table 14 and Table 23. Edited Table 15 and Table 16. Edited Table 24. Added note 2 to
Table 25, and moved RXOOBVDPP to Table 12. Added conditions to TDJ and TRJ in
Table 26. Moved TXOOBVDPP to Table 12. Added RSDS to Table 27. Added note 4 to
Table 49. Added Production Stepping section.
09/28/05
1.10
Table 2: Removed Note 1. Recommended maximum voltage drop for VCCAUX is 10 mV/ms.
相关PDF资料
PDF描述
XC4VLX15-12FFG676C FPGA, 1536 CLBS, 1205 MHz, PBGA676
XC4VFX100-10FF1152I FPGA, 10544 CLBS, 1028 MHz, PBGA1152
XC4VFX100-10FF1517I FPGA, 10544 CLBS, 1028 MHz, PBGA1517
XC4VFX100-11FF1152I FPGA, 10544 CLBS, 1181 MHz, PBGA1152
XC4VFX100-11FF1517I FPGA, 10544 CLBS, 1181 MHz, PBGA1517
相关代理商/技术参数
参数描述
XC4VLX15-11SF363C 制造商:Xilinx 功能描述:FPGA VIRTEX-4 13824 CELLS 90NM 1.2V 363FCBGA - Trays
XC4VLX15-11SF363I 功能描述:IC FPGA VIRTEX-4LX 363FCBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Virtex®-4 LX 产品变化通告:Step Intro and Pkg Change 11/March/2008 标准包装:1 系列:Virtex®-5 SXT LAB/CLB数:4080 逻辑元件/单元数:52224 RAM 位总计:4866048 输入/输出数:480 门数:- 电源电压:0.95 V ~ 1.05 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:1136-BBGA，FCBGA 供应商设备封装:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC4VLX15-11SFG363C 功能描述:IC FPGA VIRTEX-4 LX 15K 363FCBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Virtex®-4 LX 产品变化通告:Step Intro and Pkg Change 11/March/2008 标准包装:1 系列:Virtex®-5 SXT LAB/CLB数:4080 逻辑元件/单元数:52224 RAM 位总计:4866048 输入/输出数:480 门数:- 电源电压:0.95 V ~ 1.05 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:1136-BBGA，FCBGA 供应商设备封装:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC4VLX15-11SFG363I 功能描述:IC FPGA VIRTEX-4 LX 15K 363FCBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Virtex®-4 LX 产品变化通告:Step Intro and Pkg Change 11/March/2008 标准包装:1 系列:Virtex®-5 SXT LAB/CLB数:4080 逻辑元件/单元数:52224 RAM 位总计:4866048 输入/输出数:480 门数:- 电源电压:0.95 V ~ 1.05 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:1136-BBGA，FCBGA 供应商设备封装:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC4VLX15-12FF668C 制造商:Xilinx 功能描述:FPGA VIRTEX-4 13824 CELLS 90NM 1.2V 668FCBGA - Trays
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*