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参数资料
| 型号： | XC4VLX15-11FFG676I |
| 厂商： | XILINX INC |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1536 CLBS, 1205 MHz, PBGA676 |
| 封装： | LEAD FREE, FBGA-676 |
| 文件页数： | 33/58页 |
| 文件大小： | 1863K |
| 代理商： | XC4VLX15-11FFG676I |
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Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
39
CLKOUT_FREQ_FX_HF_MS_MIN
CLKFX, CLKFX180
210
MHz
CLKOUT_FREQ_FX_HF_MS_MAX
350
315
300
MHz
Input Clocks (High Frequency Mode)
CLKIN_FREQ_DLL_HF_MS_MIN(6)
CLKIN (using DLL outputs only)(1,3,4,5)
150
MHz
CLKIN_FREQ_DLL_HF_MS_MAX
500
450
400
MHz
CLKIN_FREQ_FX_HF_MS_MIN
CLKIN (using DFS outputs)(2,3,4)
50
MHz
CLKIN_FREQ_FX_HF_MS_MAX(6)
350
315
300
MHz
PSCLK_FREQ_HF_MS_MIN
PSCLK
111
KHz
PSCLK_FREQ_HF_MS_MAX
500
450
400
MHz
Notes:
1.
DLL outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2.
DFS outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3.
When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled.
4.
When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55 to
55/45).
5.
The DCM must be reset if the clock input clock stops for more than 100 ms.
6.
These values also apply when using both DLL and DFS outputs.
Table 45: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode (Continued)
Symbol
Description
Speed Grade
Units
-12
-11
-10
Table 46: Operating Frequency Ranges for DCM in Maximum Range (MR) Mode
Symbol
Description
Speed Grade
Units
-12
-11
-10
Outputs Clocks (Low Frequency Mode)
CLKOUT_FREQ_1X_LF_MR_MIN
CLK0, CLK90, CLK180, CLK270
19
MHz
CLKOUT_FREQ_1X_LF_MR_MAX
40
36
32
MHz
CLKOUT_FREQ_2X_LF_MR_MIN
CLK2X, CLK2X180
38
MHz
CLKOUT_FREQ_2X_LF_MR_MAX
80
72
64
MHz
CLKOUT_FREQ_DV_LF_MR_MIN
CLKDV
1.2
MHz
CLKOUT_FREQ_DV_LF_MR_MAX
26.7
24
21.3
MHz
CLKOUT_FREQ_FX_LF_MR_MIN
CLKFX, CLKFX180
19
MHz
CLKOUT_FREQ_FX_LF_MR_MAX
40
36
32
MHz
Input Clocks (Low Frequency Mode)
CLKIN_FREQ_DLL_LF_MR_MIN
CLKIN (using DLL outputs)(1,3,4,5,6)
19
MHz
CLKIN_FREQ_DLL_LF_MR_MAX
40
36
32
MHz
CLKIN_FREQ_FX_LF_MR_MIN
CLKIN (using DFS outputs only)(2,3,4)
111
MHz
CLKIN_FREQ_FX_LF_MR_MAX
35
32
28
MHz
PSCLK_FREQ_LF_MR_MIN
PSCLK
111
KHz
PSCLK_FREQ_LF_MR_MAX
262.50
236.30
210.00
MHz
Notes:
1.
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3.
When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled.
4.
When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55 to
55/45).
5.
The DCM must be reset if the clock input clock stops for more than 100 ms.
6.
These values also apply when using both DLL and DFS outputs.
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