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参数资料
型号： XC4VLX15-11FFG676I
厂商： XILINX INC
元件分类： FPGA
英文描述： FPGA, 1536 CLBS, 1205 MHz, PBGA676
封装： LEAD FREE, FBGA-676
文件页数： 26/58页
文件大小： 1863K
代理商： XC4VLX15-11FFG676I
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
32
CLB Distributed RAM Switching Characteristics (SLICEM Only)
)
CLB Shift Register Switching Characteristics (SLICEM Only)
)
Table 38: CLB Distributed RAM Switching Characteristics
Symbol
Description
Speed Grade
Units
-12
-11
-10
XC4VFX(2)
XC4VLX/SX
ALL DEVICES
Sequential Delays
TSHCKO
Clock CLK to X outputs (WE active)(3)
1.61
1.58
1.77
2.08
ns, Max
TSHCKOF5
Clock CLK to F5 output (WE active)
1.53
1.50
1.69
1.98
ns, Max
Setup and Hold Times Before/After Clock CLK
TDS / TDH
BX/BY data inputs (DI)
1.26
–0.90
1.23
–0.88
1.46
–0.88
1.80
–0.88
ns, Min
TAS / TAH
F/G address inputs
0.88
–0.37
0.86
–0.37
0.97
–0.34
1.13
–0.29
ns, Min
TWS / TWH
WE input (SR)
1.10
–0.48
1.08
–0.47
1.21
–0.47
1.42
–0.47
ns, Min
Clock CLK
TWPH
Minimum Pulse Width, High
0.53
0.52
0.59
0.69
ns, Min
TWPL
Minimum Pulse Width, Low
0.55
0.54
0.60
0.70
ns, Min
TWC
Minimum clock period to meet address write cycle time
0.76
0.74
0.84
0.98
ns, Min
Notes:
1.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
2.
The values in this column apply to all XC4VFX -12 parts except XC4VFX12 -12. For XC4VFX12 -12 values, use the values in the adjacent
XC4VLX/SX -12 column.
3.
TSHCKO also represents the CLK to XMUX output. Refer to TRCE report for the CLK to XMUX path.
Table 39: CLB Shift Register Switching Characteristics
Symbol
Description
Speed Grade
Units
-12
-11
-10
XC4VFX(2)
XC4VLX/SX
XC4VFX(3)
XC4VLX/SX
ALL
Sequential Delays
TREG
Clock CLK to X/Y outputs
2.12
2.08
2.19
2.57
ns, Max
TREGXB
Clock CLK to XB output via MC15 LUT output
1.83
1.73
1.90
1.84
2.16
ns, Max
TREGYB
Clock CLK to YB output via MC15 LUT output
1.84
1.74
1.92
1.85
2.17
ns, Max
TCKSH
Clock CLK to Shiftout
1.70
1.60
1.76
1.70
1.99
ns, Max
TREGF5
Clock CLK to F5 output
2.05
2.01
2.11
2.47
ns, Max
Setup and Hold Times Before/After Clock CLK
TWS / TWH
WE input (SR)
0.87
–0.76
0.85
–0.76
0.96
–0.70
0.96
–0.70
1.12
–0.62
ns, Min
TDS / TDH
BX/BY data inputs (DI)
1.28
–1.12
1.25
–1.11
1.45
–1.11
1.45
–1.11
1.75
–1.11
ns, Min
Clock CLK
TWPH
Minimum Pulse Width, High
0.53
0.52
0.59
0.69
ns, Min
TWPL
Minimum Pulse Width, Low
0.55
0.54
0.60
0.70
ns, Min
Notes:
1.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
2.
The values in this column apply to all XC4VFX -12 parts except XC4VFX12 -12. For XC4VFX12 -12 values, use the values in the adjacent
XC4VLX/SX -12 column.
3.
The values in this column apply to all XC4VFX -11 parts.
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