参数资料
型号: XRT75R12DIB-L
厂商: Exar Corporation
文件页数: 113/133页
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 12CH 420TBGA
标准包装: 40
类型: 线路接口装置(LIU)
驱动器/接收器数: 12/12
规程: DS3,E3,STS-1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 420-LBGA 裸露焊盘
供应商设备封装: 420-TBGA(35x35)
包装: 托盘
XRT75R12D
76
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
TABLE 33: XRT75R12D REGISTER MAP SHOWING TRANSMIT CONTROL REGISTERS (TC_N) (N = [0:11])
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Internal
Transmit
Drive Monitor
Insert PRBS
Error
Reserved
TAOS
TxCLKINV
TxLEV
R/W
TRANSMIT CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM4 (M = 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
7 - 6
Reserved
5
Internal Transmit
Drive Monitor
Enable
R/W
Internal Transmit Drive Monitor Enable - Channel_n:
This READ/WRITE bit-field is used to configure the Transmit Section of
Channel_n to either internally or externally monitor the TTIP_n and
TRING_n output pins for bipolar pulses, in order to determine whether to
declare the Transmit DMO Alarm condition.
If the user configures the Transmit Section to externally monitor the TTIP_n
and TRING_n output pins (for bipolar pulses) then the user must connect
the MTIP_n and MRING_n input pins to their corresponding TTIP_n and
TRING_n output pins (via a 270 ohm series resistor).
If the user configures the Transmit Section to internally monitor the TTIP_n
and TRING_n output pins (for bipolar pulses), the user does NOT need to
conect the MTIP_n and MRING_n input pins. This monitoring will be per-
formed internally at the TTIP_n and TRING_n pads.
0 - Configures the Transmit Drive Monitor to externally monitor the TTIP_n
and TRING_n output pins for bipolar pulses.
1 - Configures the Transmit Drive Monitor to internally monitor the TTIP_n
and TRING_n output pins for bipolar pulses.
4
Insert PRBS Error
R/W
Insert PRBS Error - Channel_n:
A "0 to 1" transition within this bit-field causes the PRBS Generator (within
the Transmit Section of Channel_n) to generate a single bit error within the
outbound PRBS pattern-stream.
NOTES:
1.
This bit-field is only active if the PRBS Generator and Receiver
have been enabled within the corresponding Channel.
2.
After writing the "1" into this register, the user must execute a write
operation to clear this particular register bit to "0" in order to
facilitate the next "0 to 1" transition in this bit-field.
3
Reserved
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