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型号： XRT75R12DIB-L
厂商： Exar Corporation
文件页数： 8/133页
文件大小： 0K
描述： IC LIU E3/DS3/STS-1 12CH 420TBGA
标准包装： 40
类型： 线路接口装置（LIU）
驱动器/接收器数： 12/12
规程： DS3，E3，STS-1
电源电压： 3.135 V ~ 3.465 V
安装类型： 表面贴装
封装/外壳： 420-LBGA 裸露焊盘
供应商设备封装： 420-TBGA（35x35）
包装： 托盘
XRT75R12D
101
REV. 1.0.3
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
8.3
Jitter/Wander due to Pointer Adjustments
In the previous section, we described how a DS3 signal is asynchronously-mapped into SONET, and we also
defined "Mapping/De-mapping" jitter. In this section, we will describe how occurrences within the SONET
network will induce jitter/wander within the DS3 signal that is being transported across the SONET network.
In order to accomplish this, we will discuss the following topics in detail.
The concept of an STS-1 SPE pointer
The concept of Pointer Adjustments
The causes of Pointer Adjustments
How Pointer Adjustments induce jitter/wander within a DS3 signal being transported by that SONET network.
8.3.1
The Concept of an STS-1 SPE Pointer
As mentioned earlier, the STS-1 SPE is not aligned to the STS-1 frame boundaries and is permitted to "float"
within the Envelope Capacity.
As a consequence, the STS-1 SPE will often times "straddle" across two
consecutive STS-1 frames.
Figure 48 presents an illustration of an STS-1 SPE straddling across two
consecutive STS-1 frames.
A PTE that is receiving and terminating an STS-1 data-stream will perform the following tasks.
It will acquire and maintain STS-1 frame synchronization with the incoming STS-1 data-stream.
Once the PTE has acquired STS-1 frame synchronization, then it will locate the J1 byte (e.g., the very byte
within the very next STS-1 SPE) within the Envelope Capacity by reading out the contents of the H1 and H2
bytes.
The H1 and H2 bytes are referred to (in the SONET standards) as the SPE Pointer Bytes. When these two
bytes are concatenated together in order to form a 16-bit word (with the H1 byte functioning as the "Most
Significant Byte") then the contents of the "lower" 10 bit-fields (within this 16-bit word) reflects the location of
the J1 byte within the Envelope Capacity of the incoming STS-1 data-stream.
Figure 49 presents an
illustration of the bit format of the H1 and H2 bytes, and indicates which bit-fields are used to reflect the
location of the J1 byte.
FIGURE 48. AN ILLUSTRATION OF AN STS-1 SPE STRADDLING ACROSS TWO CONSECUTIVE STS-1 FRAMES
TOH
STS-1 FRAME N
STS-1 FRAME N + 1
J1 Byte (1st byte of SPE)
J1 Byte (1st byte of next SPE)
H1, H2
Bytes
SPE can straddle across two STS-1 frames
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