参数资料
型号: XRT75R12DIB-L
厂商: Exar Corporation
文件页数: 27/133页
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 12CH 420TBGA
标准包装: 40
类型: 线路接口装置(LIU)
驱动器/接收器数: 12/12
规程: DS3,E3,STS-1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 420-LBGA 裸露焊盘
供应商设备封装: 420-TBGA(35x35)
包装: 托盘
XRT75R12D
118
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
c. Configure each of the channels within the LIU to operate in the SONET De-Sync Mode
The user can accomplish this by executing of the following step.
If the LIU has been configured to operate in the Host Mode
Then the user should clear Bit D2 (JA1) to "0" and set Bit D0 (JA0) to "1", within the Jitter Attenuator Control
Register, as depicted below.
Once the user accomplishes this step, then the Jitter Attenuator (within the LIU) will be configured to operate
with a very narrow bandwidth.
d. Configure the Jitter Attenuator (within each of the channels) to operate in the Transmit Direction.
The user can accomplish this by executing the following step.
If the LIU has been configured to operate in the Host Mode.
Then the user should set Bit D1 (JATx/JARx*) to "1", within the Jitter Attenuator Control Register, as depicted
below.
e. Enable the "SONET APS Recovery Time" Mode
Finally, if the user intends to use the LIU in an Application that is required to reacquire proper SONET and DS3
traffic, prior within 50ms of an APS (Automatic Protection Switching) event (per Telcordia GR-253-CORE), then
the user should clear Bit 4 (SONET APS Recovery Time Disable), within the "Jitter Attenuator Control"
Register, to "0" as depicted below.
TABLE 47: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL N, ADDRESS LOCATION; 0XM7
(M = 0-5 & 8-D) (N = [0:11])
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
SONET APS
Recovery
Time
DisableCh_n
JA RESET
Ch_n
JA1 Ch_n
JA in Tx Path
Ch_n
JA0 Ch_n
R/O
R/W
0
1
TABLE 48: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL N, ADDRESS LOCATION; 0XM7
(M = 0-5 & 8-D) (N = [0:11])
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
SONET APS
Recovery
Time
DisableCh_n
JA RESET
Ch_n
JA1 Ch_n
JA in Tx Path
Ch_n
JA0 Ch_n
R/O
R/W
0
1
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