参数资料
型号: XRT75R12DIB-L
厂商: Exar Corporation
文件页数: 90/133页
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 12CH 420TBGA
标准包装: 40
类型: 线路接口装置(LIU)
驱动器/接收器数: 12/12
规程: DS3,E3,STS-1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 420-LBGA 裸露焊盘
供应商设备封装: 420-TBGA(35x35)
包装: 托盘
XRT75R12D
IV
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
FIGURE 56. ILLUSTRATION OF BURST OF POINTER ADJUSTMENT SCENARIO ......................................................................................... 110
8.5.4 PHASE TRANSIENTS............................................................................................................................................... 110
FIGURE 57. ILLUSTRATION OF "PHASE-TRANSIENT" POINTER ADJUSTMENT SCENARIO .......................................................................... 110
8.5.5 87-3 PATTERN .......................................................................................................................................................... 111
FIGURE 58. AN ILLUSTRATION OF THE 87-3 CONTINUOUS POINTER ADJUSTMENT PATTERN .................................................................. 111
8.5.6 87-3 ADD ................................................................................................................................................................... 111
FIGURE 59. ILLUSTRATION OF THE 87-3 ADD POINTER ADJUSTMENT PATTERN..................................................................................... 112
8.5.7 87-3 CANCEL ............................................................................................................................................................ 112
FIGURE 60. ILLUSTRATION OF 87-3 CANCEL POINTER ADJUSTMENT SCENARIO .................................................................................... 112
8.5.8 CONTINUOUS PATTERN ......................................................................................................................................... 113
FIGURE 61. ILLUSTRATION OF CONTINUOUS PERIODIC POINTER ADJUSTMENT SCENARIO .................................................................... 113
8.5.9
CONTINUOUS ADD ................................................................................................................................................. 113
FIGURE 62. ILLUSTRATION OF CONTINUOUS-ADD POINTER ADJUSTMENT SCENARIO ............................................................................. 114
8.5.10 CONTINUOUS CANCEL ......................................................................................................................................... 114
FIGURE 63. ILLUSTRATION OF CONTINUOUS-CANCEL POINTER ADJUSTMENT SCENARIO ....................................................................... 114
8.6 A REVIEW OF THE DS3 WANDER REQUIREMENTS PER ANSI T1.105.03B-1997. ................................ 115
8.7 A REVIEW OF THE INTRINSIC JITTER AND WANDER CAPABILITIES OF THE LIU IN A TYPICAL SYSTEM
APPLICATION .............................................................................................................................................. 115
8.7.1 INTRINSIC JITTER TEST RESULTS........................................................................................................................ 115
TABLE 44: SUMMARY OF "CATEGORY I INTRINSIC JITTER TEST RESULTS" FOR SONET/DS3 APPLICATIONS ......................................... 115
8.7.2 WANDER MEASUREMENT TEST RESULTS.......................................................................................................... 116
8.8 DESIGNING WITH THE LIU ......................................................................................................................... 116
8.8.1 HOW TO DESIGN AND CONFIGURE THE LIU TO PERMIT A SYSTEM TO MEET THE ABOVE-MENTIONED INTRIN-
SIC JITTER AND WANDER REQUIREMENTS........................................................................................................... 116
FIGURE 64. ILLUSTRATION OF THE LIU BEING CONNECTED TO A MAPPER IC FOR SONET DE-SYNC APPLICATIONS .............................. 116
TABLE 45: CHANNEL CONTROL REGISTER - CHANNEL N, ADDRESS LOCATION; 0XM6 (M = 0-5 & 8-D) (N = [0:11]) ............................... 117
TABLE 46: CHANNEL CONTROL REGISTER - CHANNEL N, ADDRESS LOCATION; 0XM6 (M = 0-5 & 8-D) (N = [0:11]) ............................... 117
TABLE 47: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL N, ADDRESS LOCATION; 0XM7........................................................... 118
TABLE 48: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL N, ADDRESS LOCATION; 0XM7........................................................... 118
TABLE 49: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL N, ADDRESS LOCATION; 0XM7........................................................... 119
8.8.2 RECOMMENDATIONS ON PRE-PROCESSING THE GAPPED CLOCKS (FROM THE MAPPER/ASIC DEVICE) PRIOR
TO ROUTING THIS DS3 CLOCK AND DATA-SIGNALS TO THE TRANSMIT INPUTS OF THE LIU ...................... 119
FIGURE 65. ILLUSTRATION OF MINOR PATTERN P1 ......................................................................................................................... 120
FIGURE 66. ILLUSTRATION OF MINOR PATTERN P2 ......................................................................................................................... 120
FIGURE 67. ILLUSTRATION OF PROCEDURE WHICH IS USED TO SYNTHESIZE MAJOR PATTERN A....................................................... 121
FIGURE 68. ILLUSTRATION OF MINOR PATTERN P3 ......................................................................................................................... 121
FIGURE 69. ILLUSTRATION OF PROCEDURE WHICH IS USED TO SYNTHESIZE PATTERN B ................................................................... 122
FIGURE 70. ILLUSTRATION OF THE SUPER PATTERN WHICH IS OUTPUT VIA THE "OC-N TO DS3" MAPPER IC ................................... 122
FIGURE 71. SIMPLE ILLUSTRATION OF THE LIU BEING USED IN A SONET DE-SYNCHRONIZER" APPLICATION......................................... 123
8.8.3 HOW DOES THE LIU PERMIT THE USER TO COMPLY WITH THE SONET APS RECOVERY TIME REQUIREMENTS
OF 50MS (PER TELCORDIA GR-253-CORE)? .......................................................................................................... 123
TABLE 50: MEASURED APS RECOVERY TIME AS A FUNCTION OF DS3 PPM OFFSET ............................................................................. 123
TABLE 51: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL N, ADDRESS LOCATION; 0XM7........................................................... 124
8.8.4 HOW SHOULD ONE CONFIGURE THE LIU, IF ONE NEEDS TO SUPPORT "DAISY-CHAIN" TESTING AT THE END
CUSTOMER'S SITE? ................................................................................................................................................... 124
TABLE 52: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL N, ADDRESS LOCATION; 0XM7........................................................... 125
9.0 ELECTRICAL CHARACTERISTICS ..................................................................................................126
TABLE 53: ABSOLUTE MAXIMUM RATINGS ........................................................................................................................................... 126
TABLE 54: DC ELECTRICAL CHARACTERISTICS:................................................................................................................................... 126
ORDERING INFORMATION .................................................................................................................128
PACKAGE DIMENSIONS - ............................................................................................................................................ 128
REVISION HISTORY .................................................................................................................................................... 129
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