XRT75R12DIB-L (Exar) PDF资料下载 Datasheet(16/133 页)

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参数资料

型号：	XRT75R12DIB-L
厂商：	Exar Corporation
文件页数：	16/133页
文件大小：	0K
描述：	IC LIU E3/DS3/STS-1 12CH 420TBGA
标准包装：	40
类型：	线路接口装置（LIU）
驱动器/接收器数：	12/12
规程：	DS3，E3，STS-1
电源电压：	3.135 V ~ 3.465 V
安装类型：	表面贴装
封装/外壳：	420-LBGA 裸露焊盘
供应商设备封装：	420-TBGA（35x35）
包装：	托盘

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XRT75R12D

108

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

REV. 1.0.3

In this application, these Mapper devices can be thought of as multi-channel devices. For example, an STS-3

Mapper can be viewed as a 3-Channel DS3/STS-1 to STS-3 Mapper IC. Similarly, an STS-12 Mapper can be

viewed as a 12-Channel DS3/STS-1 to STS-12 Mapper IC. Continuing on with this line of thought, if a Mapper

IC is configured to receive an STS-N signal, and (from this STS-N signal) de-map and output N DS3 signals

(towards the DS3 facility), then it will typically do so in the following manner.

In many cases, the Mapper IC will output this DS3 signal, using both a "Data-Signal" and a "Clock-Signal".

In many cases, the Mapper IC will output the contents of an entire STS-1 data-stream via the Data-Signal.

However, as the Mapper IC output this STS-1 data-stream, it will typically supply clock pulses (via the Clock-

Signal output) coincident to whenever a DS3 bit is being output via the Data-Signal. In this case, the Mapper

IC will NOT supply a clock pulse coincident to when a TOH, POH, or any "non-DS3 data-bit" is being output

via the "Data-Signal".

Now, since the Mapper IC will output the entire STS-1 data stream (via the Data-Signal), the output Clock-

Signal will be of the form such that it has a period of 19.3ns (e.g., a 51.84MHz clock signal). However, the

Mapper IC will still generate approximately 44,736,000 clock pulses during any given one second period.

Hence, the clock signal that is output from the Mapper IC will be a horribly gapped 44.736MHz clock signal.

One can view such a clock signal as being a very-jittery 44.736MHz clock signal. This jitter that exists within

the "Clock-Signal" is referred to as "Clock-Gapping" Jitter. A more detailed discussion on how the user must

handle this type of jitter is presented in “Section 8.8.2, Recommendations on Pre-Processing the Gapped

Clocks (from the Mapper/ASIC Device) prior to routing this DS3 Clock and Data-Signals to the Transmit

Inputs of the LIU” on page 119.

8.5

A Review of the Category I Intrinsic Jitter Requirements (per Telcordia GR-253-CORE) for DS3

applications

The "Category I Intrinsic Jitter Requirements" per Telcordia GR-253-CORE (for DS3 applications) mandates

that the user perform a large series of tests against certain specified "Scenarios". These "Scenarios" and their

corresponding requirements is summarized in Table 43, below.

TABLE 43: SUMMARY OF "CATEGORY I INTRINSIC JITTER REQUIREMENT PER TELCORDIA GR-253-CORE, FOR DS3

APPLICATIONS

SCENARIO

DESCRIPTION

SCENARIO

NUMBER

TELCORDIA GR-253-CORE

CATEGORY I INTRINSIC

JITTER REQUIREMENTS

COMMENTS

DS3 De-Mapping

Jitter

0.4UI-pp

Includes effects of De-Mapping and Clock Gapping Jit-

ter

Single Pointer

Adjustment

0.3UI-pp + Ao