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| 型号： | ZL6105ALAFTK |
| 厂商： | Intersil |
| 文件页数： | 12/35页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 36-QFN |
| 标准包装： | 1,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.4MHz |
| 占空比： | 95% |
| 电源电压： | 3 V ~ 14 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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ZL6105
Power Conversion Functional
Description
TABLE 2. OUTPUT VOLTAGE PIN-STRAP SETTINGS
V0
Internal Bias Regulators and Input Supply
Connections
The ZL6105 employs two internal low dropout (LDO) regulators to
supply bias voltages for internal circuitry, allowing it to operate
V1
LOW
OPEN
HIGH
LOW
0.6V
1.2V
2.5V
OPEN
0.8V
1.5V
3.3V
HIGH
1.0V
1.8V
5.0V
from a single input supply. The internal bias regulators are as
indicated in the following:
VR - The VR LDO provides a regulated 5V bias supply for the
MOSFET driver circuits. It is powered from the VDD pin. A 4.7μF
filter capacitor is required at the VR pin.
V25 - The V25 LDO provides a regulated 2.5V bias supply for
the main controller circuitry. It is powered from an internal 5V
node. A 10μF filter capacitor is required at the V25 pin.
When the input supply (VDD) is higher than 5.5V, the VR pin should
not be connected to any other pins. It should only have a filter
The resistor setting method can be used to set the output voltage
to levels not available in Table 2. Resistors R 0 and R 1 are
selected to produce a specific voltage between 0.6V and 5.0V in
10mV steps. Resistor R 1 provides a coarse setting and resistor
R 0 provides a fine adjustment, thus eliminating the additional
errors associated with using two 1% resistors (this typically adds
approximately 1.4% error).
To set V OUT using resistors, follow the steps indicated to calculate
an index value and then use Table 3 to select the resistor that
corresponds to the calculated index value as follows:
capacitor attached as shown in Figure 8. Due to the dropout voltage
associated with the VR bias regulator, the VDD pin must be
connected to the VR pin for designs operating from a supply below
5.5V. Figure 8 illustrates the required connections for both cases.
1. Calculate Index1:
Index1 = 4 x VOUT (VOUT in 10mV steps)
2. Round the result down to the nearest whole number.
(EQ. 2)
V IN
V IN
3. Select the value of R 1 from Table 3 using the Index1 rounded
value from step 2.
ZL
VDD
ZL
VDD
4. Calculate Index0:
Index0 = 100 x VOUT - (25 x Index1)
(EQ. 3)
VR
VR
5. Select the value of R 0 from Table 3 using the Index0 value
from step 4.
3V ≤ V IN ≤ 5.5V 5.5V <V IN ≤ 14V
FIGURE 8. INPUT SUPPLY CONNECTIONS
TABLE 3. OUTPUT VOLTAGE RESISTORS SETTINGS
R0 OR R1 R0 OR R1
Note: the internal bias regulators are not designed to be outputs
for powering other circuitry. Do not attach external loads to any of
these pins. The multi-mode pins may be connected to the V25
pin for logic HIGH settings.
High-side Driver Boost Circuit
The gate drive voltage for the high-side MOSFET driver is
generated by a floating bootstrap capacitor, CB (see Figure 5).
When the lower MOSFET (QL) is turned on, the SW node is pulled
to ground and the capacitor is charged from the internal VR bias
regulator through diode DB. When QL turns off and the upper
MOSFET (QH) turns on, the SW node is pulled up to V DD and the
voltage on the bootstrap capacitor is boosted approximately 5V
above V DD to provide the necessary voltage to power the
high-side driver. A Schottky diode should be used for DB to help
maximize the high-side drive supply voltage.
Output Voltage Selection
STANDARD MODE
INDEX
0
1
2
3
4
5
6
7
8
9
10
11
12
(k Ω )
10
11
12.1
13.3
14.7
16.2
17.8
19.6
21.5
23.7
26.1
28.7
31.6
INDEX
13
14
15
16
17
18
19
20
21
22
23
24
(k Ω )
34.8
38.3
42.2
46.4
51.1
56.2
61.9
68.1
75
82.5
90.9
100
The output voltage may be set to any voltage between 0.6V and
5.0V provided that the input voltage is higher than the desired
output voltage by an amount sufficient to prevent the device
from exceeding its maximum duty cycle specification. Using the
pin-strap method, V OUT can be set to any of nine standard
voltages as shown in Table 2.
12
Example from Figure 9: For V OUT = 1.33V,
Index1 = 4 x 1.33V = 5.32;
From Table 3, R 1 = 16.2k Ω
Index0 = (100 x 1.33V) – (25 x 5) = 8;
From Table 3, R 0 = 21.5k Ω
FN6906.5
December 19, 2013
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL6105ALAFTKR5546 | 功能描述:DC/DC 开关控制器 RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| ZL6105ALAFTKR5549 | 制造商:Intersil Corporation 功能描述:ADAPTIVE DIGITAL DC-DC CONTROLLER W/ DRIVERS & I-SHARING FE0 - Tape and Reel |
| ZL6105ALAFTKR5553 | 制造商:Intersil Corporation 功能描述:ADAPTIVE DIGITAL DC-DC CONTROLLER W/ DRIVERS & I-SHARING MOD - Tape and Reel |
| ZL6105ALAFTKR5554 | 制造商:Intersil Corporation 功能描述:ADAPTIVE DIGITAL DC-DC CONTROLLER W/ DRIVERS & I-SHARING MOD - Tape and Reel |
| ZL6105ALAFTR5546 | 功能描述:IC REG CTRLR BUCK PWM VM 36-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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