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| 型号： | ZL6105ALAFTK |
| 厂商： | Intersil |
| 文件页数： | 25/35页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 36-QFN |
| 标准包装： | 1,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.4MHz |
| 占空比： | 95% |
| 电源电压： | 3 V ~ 14 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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ZL6105
2. Ratiometric . This mode configures the ZL6105 to ramp its
output voltage at a rate that is a percentage of the voltage
applied to the VTRK pin. The default setting is 50%, but an
external resistor string may be used to configure a different
tracking ratio.
Figure 15 illustrates the typical connection and the two tracking
modes.
The master ZL6105 device in a tracking group is defined as the
device that has the highest target output voltage within the
group. This master device will control the ramp rate of all
tracking devices and is not configured for tracking mode. A delay
of at least 10ms must be configured into the master device using
the SS pin, and the user may also configure a specific ramp rate
R SS
(k Ω )
90.9
100
110
121
133
TABLE 20. TRACKING RESISTOR SETTINGS
TRACK
RATIO UPPER TRACK
(%) LIMIT RAMP-UP/DOWN BEHAVIOR
Output does not decrease
Limited by target before PG
Output always follows VTRK
100
Output does not decrease
Limited by VTRK before PG
Output always follows VTRK
Output does not decrease
Limited by target before PG
using the SS pin. Any device that is configured for tracking mode
will ignore its soft-start delay and ramp time settings (SS pin) and
its output will take on the turn-on/turn-off characteristics of the
reference voltage present at the VTRK pin. All of the ENABLE pins
in the tracking group must be connected together and driven by a
single logic source. Tracking is configured via the I 2 C/SMBus
interface by using the TRACK_CONFIG PMBus command. Please
refer to Application Note AN2033 for more information on
configuring tracking mode using PMBus.
When a current sharing rail is tracking, the on-delay time of the
voltage being tracked must not exceed the on-delay of the
tracking rail by 5ms.
V IN
147 Output always follows VTRK
50
162 Output does not decrease
Limited by VTRK before PG
178 Output always follows VTRK
Voltage Margining
The ZL6105 offers a simple means to vary its output higher or
lower than its nominal voltage setting in order to determine
whether the load device is capable of operating over its specified
supply voltage range. The MGN command is set by driving the
MGN pin or through the I 2 C/SMBus interface. The MGN pin is a
tri-level input that is continuously monitored and can be driven
directly by a processor I/O pin or other logic-level output.
The ZL6105’s output will be forced higher than its nominal set
GH
Q1
point when the MGN command is set HIGH, and the output will
V TRK
ZL
SW
GL
Q2
L1
V OUT
C1
be forced lower than its nominal set point when the MGN
command is set LOW. Default margin limits of V NOM ±5% are
pre-loaded in the factory, but the margin limits can be modified
through the I 2 C/SMBus interface to as high as V NOM + 10% or as
low as 0V, where V NOM is the nominal output voltage set point
determined by the V0 and V1 pins. The ZL6105-01 allows 150%
V OUT
Coincident
V TRK
V OUT
Time
margin limits.
The margin limits and the MGN command can both be set
individually through the I 2 C/SMBus interface. Additionally, the
transition rate between the nominal output voltage and either
margin limit can be configured through the I 2 C interface. Please
refer to Application Note AN2033 for detailed instructions on
modifying the margining configurations.
I 2 C/SMBus Communications
The ZL6105 provides an I 2 C/SMBus digital interface that enables
the user to configure all aspects of the device operation as well
V OUT
Ratiometric
FIGURE 15. TRACKING MODES
25
V TRK
V OUT
Time
as monitor the input and output parameters. The ZL6105 can be
used with any standard 2-wire I 2 C host device. In addition, the
device is compatible with SMBus version 2.0 and includes an
SALRT line to help mitigate bandwidth limitations related to
continuous fault monitoring. Pull-up resistors are required on the
I 2 C/SMBus as specified in the SMBus 2.0 specification. The
ZL6105 accepts most standard PMBus commands. When
controlling the device with PMBus commands, it is
recommended that the enable pin is tied to SGND.
I 2 C/SMBus Device Address Selection
When communicating with multiple SMBus devices using the
I 2 C/SMBus interface, each device must have its own unique
FN6906.5
December 19, 2013
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL6105ALAFTKR5546 | 功能描述:DC/DC 开关控制器 RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| ZL6105ALAFTKR5549 | 制造商:Intersil Corporation 功能描述:ADAPTIVE DIGITAL DC-DC CONTROLLER W/ DRIVERS & I-SHARING FE0 - Tape and Reel |
| ZL6105ALAFTKR5553 | 制造商:Intersil Corporation 功能描述:ADAPTIVE DIGITAL DC-DC CONTROLLER W/ DRIVERS & I-SHARING MOD - Tape and Reel |
| ZL6105ALAFTKR5554 | 制造商:Intersil Corporation 功能描述:ADAPTIVE DIGITAL DC-DC CONTROLLER W/ DRIVERS & I-SHARING MOD - Tape and Reel |
| ZL6105ALAFTR5546 | 功能描述:IC REG CTRLR BUCK PWM VM 36-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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