参数资料
型号: ZL6105ALAFTK
厂商: Intersil
文件页数: 3/35页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 36-QFN
标准包装: 1,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.4MHz
占空比: 95%
电源电压: 3 V ~ 14 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 36-VFQFN 裸露焊盘
包装: 带卷 (TR)
ZL6105
Typical Application Circuit
The following application circuit represents a typical implementation of the ZL6105. For enable using the PMBus, it is recommended to
tie the enable pin (EN) to SGND.
ENABLE
F.B. 1
V IN 12V
C IN
PHASE ENABLE
4.7 μF
25 V
3 x 10 μF
25 V
POWER GOOD OUTPUT
DDC Bus 3
C V25
10 μF
4V
QH
DB
BAT54
1 μF
16 V
V25
1 DGND
2 SYNC
VDD 27
BST 26
CB
3 SA0
4 SA1
GH 25
SW 24
L OUT
V OUT
5 ILIM
ZL6105
PGND 23
2.2 μH
I 2 C/SMBus 2
6 CFG0
7 SCL
8 SDA
9 SALRT
GL 22
VR 21
ISENA 20
ISENB 19
C OUT
2 x 47 μF
6.3 V
QL
470 μF
2.5 V
POS-CAP
2*220 μF
6.3 V
100 m
EPAD
C VR
4.7 μF
6.3 V
RTN
Ground unification
Notes:
1. Ferrite bead is optional for input noise suppression
2. The I 2 C/SMBus requires pull-up resistors. Please refer to the I 2 C/SMBus specifications for more details.
3. The DDC bus requires a pull-up resistor. The resistance will vary based on the capacitive loading of the bus (and on the number of devices
connected). The 10 k ? default value, assuming a maximum of 100 pF per device, provides the necessary 1 μs pull-up rise time. Please refer to the
DDC Bus section for more details.
FIGURE 3. 12V TO 1.8V/16A APPLICATION CIRCUIT
3
FN6906.5
December 19, 2013
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ZL6105ALAFTR5546 功能描述:IC REG CTRLR BUCK PWM VM 36-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC(0.154",3.90mm 宽) 包装:带卷 (TR)