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| 型号： | ZL6105ALAFTK |
| 厂商： | Intersil |
| 文件页数： | 21/35页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 36-QFN |
| 标准包装： | 1,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.4MHz |
| 占空比： | 95% |
| 电源电压： | 3 V ~ 14 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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ZL6105
--------------------- ( in% ) ≤ ---------------------------------------
Vin Nom
256 ? Vout (EQ. 31)
Vin Nom
Loop Compensation
The ZL6105 operates as a voltage-mode synchronous buck
controller with a fixed frequency PWM scheme. Although the
ZL6105 uses a digital control loop, it operates much like a
traditional analog PWM controller. Figure 13 is a simplified block
diagram of the ZL6105 control loop, which differs from an
analog control loop only by the constants in the PWM and
compensation blocks. As in the analog controller case, the
compensation block compares the output voltage to the desired
voltage reference and compensates to keep the loop stable. The
resulting integrated error signal is used to drive the PWM logic,
converting the error signal to a duty cycle to drive the external
MOSFETs.
The ZL6105 has an auto compensation feature that measures
the characteristics of the power train and calculates the proper
tap coefficients. Auto compensation is configured using the FC0
and FC1 pins as shown in Table 16 and Table 17.
When auto compensation is enabled, the routine can be set to
execute one time after ramp or periodically while regulating.
Note that the Auto Compensation feature requires a minimum
immediately after the first Auto Comp cycle completes
(POWER_GOOD_DELAY will be ignored).
The Auto Comp Gain control scales the Auto Comp results to
allow a trade-off between transient response and steady-state
duty cycle jitter. A setting of 100% will provide the fastest
transient response while a setting of 10% will produce the lowest
jitter.
Note that if Auto Comp is enabled, for best results Vin must be
stable before Auto Comp begins, as shown in Equation 31.
Δ Vin 100%
1 + -----------------------------
The auto compensation function can also be configured via the
AUTO_COMP_CONFIG command and controlled using the
AUTO_COMP_CONTROL command over the I 2 C/SMBus interface.
Please refer to Application Note AN2033 for further details.
TABLE 16. FC0 PIN-STRAP SETTINGS
FC0 PIN
STORE VALUES
SINGLE/REPEAT
PG ASSERT
V IN
LOW
OPEN
Not Stored
Auto Comp Disabled
Single
After Auto Comp
DPWM
D
1-D
L
C
R C
R O
V OUT
HIGH
10k ?
11k ?
12.1k ?
Store in Flash
Not Stored
Store in Flash
Not Stored
Single
Single
Repeat ~1 sec
After Auto Comp
After Auto Comp
13.3k ?
Store in Flash
Compensation
14.7k ?
Not Stored
Single
FIGURE 13. CONTROL LOOP BLOCK DIAGRAM
If the device is configured to store auto comp values, the
calculated compensation values will be saved in the Auto Comp
Store and may be read back through the PID_TAPS command. If
repeat mode is enabled, the first Auto Comp results after the first
ramp will be stored; the values calculated periodically are not
stored in the Auto Comp Store. When compensation values are
saved in the Auto Comp Store, the device will use those
compensation values on subsequent ramps. In repeat mode, the
latest Auto Comp results will always be used during operation.
Stored Auto Comp results can only be cleared by disabling Auto
Comp Store, which is not permitted while the output is enabled.
However, sending the AUTOCOMP_CONTROL command while
enabled in Store mode will cause the next results to be stored,
16.2k ?
17.8k ?
19.6k ?
21.5k ?
23.7k ?
26.1k ?
28.7k ?
31.6k ?
34.8k ?
38.3k ?
42.2k ?
Store in Flash
Not Stored
Store in Flash
Not Stored
Store in Flash
Not Stored
Store in Flash
Not Stored
Store in Flash
Not Stored
Store in Flash
Repeat ~1 sec
Single
Repeat ~1 min
Single
Repeat ~1 min
After PG Delay
After Auto Comp
After PG Delay
overwriting previously stored values. If auto compensation is
disabled, the device will use the compensation parameters that
are stored in the DEFAULT_STORE or USER_STORE.
If the PG Assert parameter is set to "Use PG Delay," PG will be asserted
according to the POWER_GOOD_DELAY command, after which Auto
Comp will begin. When Auto Comp is enabled, the user must not
program a Power-Good Delay that will expire before the ramp is
finished. If PG Assert is set to "After Auto Comp," PG will be asserted
21
FN6906.5
December 19, 2013
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL6105ALAFTKR5546 | 功能描述:DC/DC 开关控制器 RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| ZL6105ALAFTKR5549 | 制造商:Intersil Corporation 功能描述:ADAPTIVE DIGITAL DC-DC CONTROLLER W/ DRIVERS & I-SHARING FE0 - Tape and Reel |
| ZL6105ALAFTKR5553 | 制造商:Intersil Corporation 功能描述:ADAPTIVE DIGITAL DC-DC CONTROLLER W/ DRIVERS & I-SHARING MOD - Tape and Reel |
| ZL6105ALAFTKR5554 | 制造商:Intersil Corporation 功能描述:ADAPTIVE DIGITAL DC-DC CONTROLLER W/ DRIVERS & I-SHARING MOD - Tape and Reel |
| ZL6105ALAFTR5546 | 功能描述:IC REG CTRLR BUCK PWM VM 36-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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