参数资料
型号: ZL6105ALAFTK
厂商: Intersil
文件页数: 13/35页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 36-QFN
标准包装: 1,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.4MHz
占空比: 95%
电源电压: 3 V ~ 14 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 36-VFQFN 裸露焊盘
包装: 带卷 (TR)
ZL6105
=
Index 0 + ( 25 × Index 1 )
V OUT
The output voltage can be determined from the R 0 (Index0) and
R 1 (Index1) values using Equation 4:
(EQ. 4)
100
TABLE 4. SINGLE RESISTOR V OUT SETTING (Continued)
R V1
(k ? ) R V0 V OUT
133 LOW 3.30
Single Resistor Output Voltage Setting Mode
Some applications desire the output voltage to be set using a
single resistor. This can be accomplished using a resistor on the
147
162
178
LOW
LOW
LOW
4.00
5.00
5.50
V1 pin while the V0 pin is tied to SGND. Table 4 lists the available
output voltage settings with a single resistor.
SMBus Mode
V IN
The output voltage may be set to any value between 0.6V and
5.0V using a PMBus command over the I 2 C/SMBus interface.
See Application Note AN2033 for details.
ZL
GH
SW
V OUT
1.33V
Start-up Procedure
V0
V1
GL
The ZL6105 follows a specific internal start-up procedure after
power is applied to the VDD pin. Table 5 describes the start-up
sequence.
R0
21. 5 k ?
R1
16.2 k ?
TABLE 4. SINGLE RESISTOR V OUT SETTING
FIGURE 9. OUTPUT VOLTAGE RESISTOR SETTING EXAMPLE
R V1
(k ? )
10
11
12.1
13.3
14.7
16.2
17.8
19.6
21.5
23.7
26.1
28.7
31.6
34.8
38.3
42.2
46.4
51.1
56.2
61.9
68.1
75
82.5
90.9
100
110
121
13
R V0
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
V OUT
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.40
1.50
1.60
1.70
1.80
1.90
2.00
2.10
2.20
2.30
2.50
3.00
If the device is to be synchronized to an external clock source, the
clock frequency must be stable prior to asserting the EN pin. The
device requires approximately 5ms to 10ms to check for specific
values stored in its internal memory. If the user has stored values
in memory, those values will be loaded. The device will then
check the status of all multi-mode pins and load the values
associated with the pin settings.
Once this process is completed, the device is ready to accept
commands via the I 2 C/SMBus interface and the device is ready
to be enabled. Once enabled, the device requires a minimum
delay period following an enable signal and prior to ramping its
output, as described in “Soft-Start Delay and Ramp Times” on
page 14. If a soft-start delay period less than the minimum has
been configured (using PMBus commands), the device will
default to the minimum delay period. If a delay period greater
than the minimum is configured, the device will wait for the
configured delay period prior to starting to ramp its output.
After the delay period has expired, the output will begin to ramp
towards its target voltage according to the pre-configured
soft-start ramp time that has been set using the SS pin. It should
be noted that if the EN pin is tied to VDD, the device will still
require approximately 5ms to 10ms before the output can begin
its ramp-up as described in Table 5.
FN6906.5
December 19, 2013
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