参数资料
型号: ZL6105ALAFTK
厂商: Intersil
文件页数: 27/35页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 36-QFN
标准包装: 1,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.4MHz
占空比: 95%
电源电压: 3 V ~ 14 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 36-VFQFN 裸露焊盘
包装: 带卷 (TR)
ZL6105
where R PU is the DDC bus pull-up resistance and C LOAD is the bus
loading. The pull-up resistor may be tied to VR or to an external
3.3V or 5V supply as long as this voltage is present prior to or
during device power-up. As rules of thumb, each device
TABLE 25. PHASE OFFSET RESISTOR SETTINGS
R CFG2 PHASE OFFSET CURRENT
(k Ω ) (°) SENSE
connected to the DDC bus presents ~10pF of capacitive loading,
and each inch of FR4 PCB trace introduces ~2pF. The ideal
design will use a central pull-up resistor that is well-matched to
the total load capacitance. In power module applications, the
user should consider whether to place the pull-up resistor on the
module or on the PCB of the end application. The minimum pull-
up resistance should be limited to a value that enables any
device to assert the bus to a voltage that will ensure a logic 0
(typically 0.8V at the device monitoring point) given the pull-up
voltage (5V if tied to VR) and the pull-down current capability of
10
11
12.1
13.3
14.7
16.2
17.8
22.5
45
67.5
90
112.5
135
157.5
the ZL6105 (nominally 4mA).
Phase Spreading
When multiple point of load converters share a common DC
input supply, it is desirable to adjust the clock phase offset of
each device such that not all devices start to switch
simultaneously. Setting each converter to start its switching cycle
at a different point in time can dramatically reduce input
capacitance requirements and efficiency losses. Since the peak
current drawn from the input supply is effectively spread out over
a period of time, the peak current drawn at any given moment is
reduced and the power losses proportional to the I RMS2 are
reduced dramatically.
In order to enable phase spreading, all converters must be
synchronized to the same switching clock. The CFG1 pin is used
to set the configuration of the SYNC pin for each device as
The phase offset of each single-phase device may be set to any
value between 0° and 337.5° in 22.5° increments using the
CFG2 pin as shown in Tables 24 and 25.
TABLE 24. PHASE OFFSET PIN-STRAP SETTINGS
PHASE OFFSET
19.6
21.5
23.7
26.1
28.7
31.6
34.8
38.3
42.2
46.4
51.1
56.2
61.9
68.1
75
82.5
90.9
180
202.5
225
247.5
270
292.5
315
337.5
22.5
45
67.5
90
112.5
135
157.5
180
202.5
DCR
RDS
R CFG2
LOW
OPEN
HIGH
(°)
90
0
180
CURRENT SENSE
DCR
100
110
121
133
225
247.5
270
292.5
27
147
162
315
337.5
FN6906.5
December 19, 2013
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