参数资料
型号: ZL6105ALAFTK
厂商: Intersil
文件页数: 33/35页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 36-QFN
标准包装: 1,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.4MHz
占空比: 95%
电源电压: 3 V ~ 14 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 36-VFQFN 裸露焊盘
包装: 带卷 (TR)
ZL6105
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
December 19, 2013
July 30, 2013
October 15, 2012
October 1, 2012
December 15, 2010
December 8, 2010
September 20, 2010
September 14, 2010
FN6906.5 Sentence after Equation 29 on page 19 changed from “The value of R 2 should be simply 5x that of R 1 as shown in
Equation 30:” to “The value of R 2 should be 2k Ω ”. Equation was deleted.
ISENA pin. The voltage rating changed from: -1.5V to 6.5V, to: -1.5V to 30V.
Changed the 6.5V to 30V on page 7 Absolute Maximum Ratings
FN6906.4 Changed POD from L36.6x6A to L36.6x6C - change in side view MAX from 0.90 to 1.00
Removed all references to ZL6105-01, page 5, Ordering Information
FN6906.3 In “Voltage Margining” on page 25, in the 2nd paragraph, changed the last sentence from "A safety feature prevents
the user from configuring the output voltage to exceed VNOM + 10% under any conditions." to "The ZL6105-01 allows
150% margin limits."
Added following parts to “Ordering Information” on page 6:
ZL6105ALAF-01
ZL6105ALAFT-01
ZL6105ALAFTK-01
Updated note in MIN, MAX column of spec table from "Parameters with MIN and/or MAX limits are 100% tested
at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production
tested." to "Compliance to datasheet limits is assured by one or more methods: production test, characterization
and/or design."
Removed note "Limits established by characterization and are not production tested." and all references to it.
FN6906.2 Added following statement to disclaimer on page 34: “This product is subject to a license from Power One, Inc.
related to digital power technology as set forth in U.S. Patent No. 7,000,125 and other related patents owned by
Power One, Inc. These license rights do not extend to stand-alone POL regulators unless a royalty is paid to Power
One, Inc.”
FN6906.1 -Added a second sentence ("A minimum droop resistance of 0.5m ? is recommended.") to “Active Current
-On page 21, in Equation 31, changed " δ " to " Δ ".
-Added “Limits established by characterization and are not production tested.” to “Soft-start Delay Duration
Range” on page 8, “Soft-start Ramp Duration Range” on page 8 and “VTRK Regulation Accuracy” on page 8.
-Removed PG and SALRT from Conditions column of “Logic Input Leakage Current” on page 8.
-Added the following paragraph to page 14:
"The ZL6105 has a minimum TON_DELAY requirement ... See Application Note AN2033 for details."
-Changed LOW delay time from "2" to "5" in Table 6 on page 14
-Removed first three rows (10, 11, and 12.1 rows) from Table 7 on page 14
-Rewrote paragraph directly above Figure 13 on page 21 (“When auto compensation is enabled ... as described
in “Soft-Start Delay and Ramp Times” on page 14")
-Changed min “Soft-start Delay Duration Range” on page 8 from 2 to 5 and 0.002 to 0.005
-Reworded Note 15 on page 9
-Changed Step 5 Description in Table 5 on page 14
-Replaced Step 5 Time Duration entry in Table 5 on page 14 with a dash (“-”)
-Rewrote paragraph on page 13 (“Once this process is completed...to ramp its output”)
-Replaced Table 16 “FC0 PIN-STRAP SETTINGS” on page 21
-Replaced Table 17 “FC1 PIN-STRAP SETTINGS” on page 22
-Rewrote the last three paragraphs of “Loop Compensation” on page 21
-Added third paragraph to “Power-Good” on page 15 (“If Auto Comp is enabled, the PG timing is further controlled
by the PG Assert parameter as described “Loop Compensation” on page 21.”)
-Added sentence to Note 17 on page 9 ("Refer to “Soft-Start Delay and Ramp Times” on page 14 for further
restrictions on PG Delay.")
-In“Soft-start Delay Duration Accuracy” on page 8, in the Conditions, changed both references to Note 16 to be
Note 15. Removed Note 16.
-Rewrote first paragraph of “Configuration B: SYNC INPUT” on page 15
-Rewrote first three paragraphs of “Configuration C: SYNC AUTO DETECT” on page 15
-Added sentence just before Table 23 on page 26 (“Note that the SMBus address 0x4B is reserved for device test
and cannot be used in the system.”)
33
FN6906.5
December 19, 2013
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ZL6105ALAFTR5546 功能描述:IC REG CTRLR BUCK PWM VM 36-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC(0.154",3.90mm 宽) 包装:带卷 (TR)