- 您现在的位置：买卖IC网 > PDF目录11767 > AD6620ASZ-REEL (Analog Devices Inc)IC DGTL RCVR DUAL 67MSPS 80-PQFP PDF资料下载
参数资料
| 型号： | AD6620ASZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 21/44页 |
| 文件大小： | 0K |
| 描述： | IC DGTL RCVR DUAL 67MSPS 80-PQFP |
| 标准包装： | 500 |
| 接口： | 并行/串行 |
| 电源电压： | 3 V ~ 3.6 V |
| 封装/外壳： | 80-BQFP |
| 供应商设备封装： | 80-PQFP（14x14） |
| 包装： | 带卷 (TR) |
| 安装类型： | 表面贴装 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页当前第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页
AD6620
–28–
REV. A
Table IX. Control Register and RAM Addresses
Address
Bit Width
Name
Notation
Description
000–0FF
20
RCF Coefficient RAM
100–1FF
36
RCF Data RAM
200–27F
0
Reserved
300
8
MODE CONTROL REGISTER
0: SOFT_RESET
1
1: Diversity Channel Real Input Mode
2: Single Channel Complex Input Mode
3: Sync Master/Slave
2 (Master = 1,
Slave = 0)
7–4: Reserved
301
3
NCO CONTROL REGISTER
0: NCO Bypass (Bypass = 1, Active = 0)
1: Enable Phase Dither
2: Enable Amplitude Dither
7–3: Reserved
302
32
NCO SYNC CONTROL REGISTER
SYNC_MASK
Write: Sync Mask Shadow
Read: Sync Mask
303
32
NCO_FREQ
Channel Frequency for NCO Tuning
304
16
NCO PHASE_OFFSET
NCO Phase Offset
305
8
INPUT/CIC2 SCALE REGISTER
2–0: SCIC2
3: Reserved
4: ExpInv
7–5: : ExpOff
306
8
MCIC2 – 1MCIC2 – 1
CIC2 Decimation Minus One
307
5
CIC5 SCALE REGISTER
SCIC5
4–0: SCIC5
7–5: Reserved
308
8
MCIC5 – 1MCIC5 – 1
CIC5 Decimation Minus One
309
4
OUTPUT/RCF CONTROL REGISTER
SOUT
2–0: Output Scale Factor
3: Unique B Flag (Normal Mode = 0,
Unique B Mode = 1)
7–4: Reserved
30A
8
MRCF – 1MRCF – 1
RCF Decimation Minus One
30B
8
RCF ADDRESS OFFSET REGISTER
RCFOFF
Filter Coefficient Address Offset
30C
8
NTAPS – 1NTAPS – 1
Number of Taps Minus One
30D
8
Reserved (Should Be Written 0)
NOTES
1This bit is set high on
RESET. The chip is held into SOFT_RESET until it is written low.
2This bit is set low on
RESET. This keeps multiple AD6620 SYNC Masters from driving each other.
outputs while acting as a sync master, or as inputs while acting
as a sync slave. This is the only register with a defined power-up
state: on power-up, Bit 0 will be at a Logic “1.” This places the
chip in SOFT_RESET and defines the chip as a sync slave.
Powering up as a sync slave avoids contention problems when
connecting multiple AD6620s.
If Bit 0 is written low and Bits 2 and 1 are low, the AD6620 is in
Single Channel Real Mode. If Bit 1 is high and Bits 0 and 2 are
low, the device is in the Diversity Channel Real Mode. If Bit 2
is high and Bits 0 and 1 are low, the chip is in the Single Chan-
nel Complex Mode. Setting Bit 3 high configures the AD6620
as a SYNC master; the SYNC pins are then used as outputs. If
Bit 3 is low, it is a SYNC slave and the SYNC pins function
as inputs. Bits 7–4 are reserved and should be written low.
(0x301) NCO Control Register
This register allows control of special features of the NCO. If
Bit 0 of this register is high the NCO of the AD6620 is by-passed.
Both the I data and the Q data that are passed through the chip
will be the same and the Spectrum will not be translated. In
bypass the input data is attenuated by 12 dB.
(0x000–0xFF) RCF Coefficient RAM
Memory that stores user-programmable coefficients for the RCF
filter. The RAM will hold 256 20-bit twos complement words
for a maximum filter length of 256 taps. In Diversity Channel
Real Mode the filter length is limited to 128 taps per channel.
The number of taps used is controlled by NTAPS–1 (30C) regard-
less of the number of coefficient locations programmed. If filter
size allows, more than one filter can be resident in the memory
at a time. This makes it possible to switch filters without reloading
all of the coefficients.
(0x100–0x1FF) RCF Data RAM
These locations store I and Q data exiting the CIC5 filter stage
while the RCF performs multiply accumulates. The lower 18
bits of the 36-bit location is I data; the upper 18 bits are Q data.
These locations are addressed in memory and are available via
the control ports so that the data RAM can be flushed for test-
ing and simulation purposes. They are not cleared on reset.
(0x300) Mode Control Register
This location brings the chip out of reset and sets the operating
mode. It also specifies how the chip will use its SYNC pins: as
相关PDF资料 |
PDF描述 |
|---|---|
| 6274291-2 | CONN JACK VERT PCB 75 OHM BNC |
| AD7669JNZ | IC I/O PORT 8BIT ANLG 28DIP |
| D38999/24FF11PA | CONN RCPT 11POS JAM NUT W/PINS |
| D38999/20JE26HN | CONN RCPT 26POS WALL MNT W/PINS |
| AD7569KNZ | IC I/O PORT 8BIT ANALOG 24DIP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6620PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor |
| AD6620S | 制造商:AD 制造商全称:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor |
| AD6620S/PCB | 制造商:Analog Devices 功能描述:DUAL CHANNEL DECIMATING RECEIV 制造商:Analog Devices 功能描述:SGNL PROCESSOR 169CSPBGA - Bulk |
| AD6622 | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622AS | 制造商:Analog Devices 功能描述:Transmit Signal Processor 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:4 CHANNEL 65 MSPS DIGITAL UPCONVERTER - Bulk |
发布紧急采购，3分钟左右您将得到回复。