参数资料
型号: AD6620ASZ-REEL
厂商: Analog Devices Inc
文件页数: 42/44页
文件大小: 0K
描述: IC DGTL RCVR DUAL 67MSPS 80-PQFP
标准包装: 500
接口: 并行/串行
电源电压: 3 V ~ 3.6 V
封装/外壳: 80-BQFP
供应商设备封装: 80-PQFP(14x14)
包装: 带卷 (TR)
安装类型: 表面贴装
AD6620
–7–
REV. A
TIMING DIAGRAMS
CLK, INPUTS, PARALLEL OUTPUTS
RESET with PAR/SER = “1” establishes Parallel Outputs active.
tCLKH
tCLKL
tCLK
CLK
Figure 3. CLK Timing Requirements
CLK
IN[15:0]
EXP[2:0]
A/B
tSI
tHI
DATA
Figure 4. Input Data Timing Requirements
CLK
OUT[15:0]
VALID OUTPUT DATA
DVOUT
I/QOUT
tDPR
tDPF
I
Q
I
Q
IA
QA
IB
QB
tDPF
Figure 5. Parallel Output Switching Characteristics
SYNC PULSES: SLAVE OR MASTER
tSY
tHY
CLK
SYNC NCO
SYNC CIC
SYNC RCF
NOTE:
IN THE SLAVE MODE WITH SINGLE CHANNEL OPERATION, THE WIDTH
OF THE SYNC_NCO SHOULD BE ONE SAMPLE CLOCK CYCLE. IN DUAL
CHANNEL MODE, THE PULSEWIDTH SHOULD BE TWO SAMPLE CLOCK
CYCLES. IF A PULSE LONGER THAN SPECIFIED IS USED, THE NCO WILL
BE INHIBITED AND NOT INCREMENT PROPERLY.
Figure 6. SYNC Slave Timing Requirements
CLK
tCHP
tCPL
tCS
tCH
IN[15:0]
E[2:0]
A/B
N+1
N
tCLK
Figure 7. SYNC Master Delay
tRESL
RESET
Figure 8. Reset Timing Requirements
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