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参数资料
| 型号： | AD6620ASZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 22/44页 |
| 文件大小： | 0K |
| 描述： | IC DGTL RCVR DUAL 67MSPS 80-PQFP |
| 标准包装： | 500 |
| 接口： | 并行/串行 |
| 电源电压： | 3 V ~ 3.6 V |
| 封装/外壳： | 80-BQFP |
| 供应商设备封装： | 80-PQFP（14x14） |
| 包装： | 带卷 (TR) |
| 安装类型： | 表面贴装 |
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AD6620
–29–
REV. A
(0x309) Output/RCF Control Register
Bits 2-0 of this register hold the Output Scale Factor, SOUT.
These bits are interpreted as a 3-bit unsigned integer, the value
of which controls which of the 23 output bits of the RCF are
passed to the output port being used. The data output corre-
sponds to the following equation where OLRCF is the 23-bit
output of the RCF and POL is the 16-bit data available at the
parallel output port or the serial port when 16-bit serial words
are used. The truncation function rounds the scaled 23-bit
number to 16 bits. SOUT is ignored when WL is 24 or 32 bits. In
most applications, this register should be set to 4 as an initial
starting value.
POL
round
OL
bits
RCF
S
OUT
=×
16
4
2
()
( –
)
For additional details on determining RCF gain, see the RCF
Output Scale Factor section.
Bit 3 of this register is used to control the Unique B feature of
the chip. When written low, the normal mode, the chip uses the
same FIR coefficients for both the A and B channels. However,
when the bit is set high, different coefficients are used for the A
and B channels. When Unique B mode is selected, the filter
coefficients should be interleaved with the A channel terms
occupying the even RCF Coefficient locations and the B chan-
nel terms occupying the odd locations.
Bits 7–4 of this register are reserved and must be written 0.
(0x30A) (MRCF – 1)
This register controls the amount of decimation in the RCF
filter stage. The value contained in this register is the RCF
decimation rate minus one. This is interpreted as an unsigned
8-bit integer, but due to limited number of taps and, therefore,
filtering power in the RCF filter accumulators this value should
be limited to 31 (decimation = 32).
(0x30B) RCF Address Offset Register
This register controls the address offset used by the RCF to
calculate a given filter and is interpreted as an 8-bit unsigned
integer. It allows more than one filter to be placed in the Coeffi-
cient RAM. This makes it possible to switch filters without
reloading all of the coefficients. The RCF filter will compute
taps for all coefficients between RCFOFF and (RCFOFF + NTAPS)
provided that the decimation, CLK rate and input data rate
provide sufficient time for this.
(0x30C) (NTAPS – 1)
This register controls the number of taps calculated by the RCF.
The value in this register is interpreted as an unsigned integer
and is equal to the number of taps desired minus one. This filter
is not inherently symmetric and the number of coefficients placed
in the Coefficient RAM will be equal to the number of taps,
provided that only one filter at a time is loaded. No symmetry is
assumed and preaddition is not used. The total number of taps
for all filters must be less than 256 taps for Single Channel
Real mode, or less than 128 taps/channel for Diversity Channel
Real mode.
(0x30D) Reserved
Reserved, but must be written 0 for correct operation.
The NCO has two features to improve the performance of some
systems: Phase Dither and Amplitude Dither. These can be used
together or alone. If Bit 1 of the register is high, Phase Dither is
activated. If Bit 2 is high, Amplitude Dither is activated. For
more information on dither refer to the NCO section.
(0x302) NCO SYNC Control Register
This holds the SYNC_MASK, which controls the frequency of
the SYNC_NCO pulses and therefore the phase accuracy of the
synchronization. See the NCO section for details.
(0x303) NCO_FREQ
This register holds the NCO frequency control word as described
in the NCO section. This is a 32-bit unsigned integer that sets
the frequency of the AD6620 NCO.
(0x304) NCO PHASE_OFFSET
This register controls the phase offset of the NCO. It is also
described in detail in the NCO section and can be used to allow
for phase differences between multiple antennas receiving the
same carrier.
(0x305) INPUT/CIC2 Scale Register
This register holds the scale factor, SCIC2, for CIC2. SCIC2 scales
down the data before it is accumulated in CIC2. This avoids
register wrap-around in the twos-complement arithmetic and
eliminates the resulting spectral errors. SCIC2 is contained in Bits
2–0 of this register. It is treated as an unsigned integer between
0 and 6. Increasing SCIC2 shifts data down. For more details
refer to the section on the CIC2 filter.
The second function of this register is to scale the input data
from the Parallel Data Input port. This allows the AD6620 to
treat the floating point input data with considerable flexibility.
There are two parts of this function. The first is Bit 4, which
tells the AD6620 how to handle the exponent, EXP[2:0]. If this
bit is low, data is shifted down as the exponent increases. If this
bit is high, then for increasing EXP[2:0] the input data is shifted
up. The second part of the input data shifting is the Exponent
Offset(ExpOff[7 . . 5]) held in Bits 7–5 of this register. This pro-
vides gain to the input data as described in the Input Port section.
(0x306) (MCIC2 – 1)
This register controls the amount of decimation in the CIC2 filter
stage. The value contained in this register is the CIC2 decima-
tion rate minus one. This is interpreted as an unsigned 8-bit
integer but due to limited growth in the CIC2 filter accumula-
tors this value should be limited to 15 (decimation = 16).
(0x307) SCIC5
This register holds the scale factor, SCIC5, for CIC5. SCIC5 scales
down the data before it is accumulated in CIC5. This avoids
register wrap-around in the twos-complement arithmetic and elimi-
nates the resulting spectral errors. SCIC5 is contained in Bits 4–0
of this register. It is treated as an unsigned integer between 0
and 20. Increasing SCIC5 shifts data down. For more details refer
to the section on the CIC5 filter.
(0x308) (MCIC5 – 1)
This register controls the amount of decimation in the CIC5
filter stage. The value contained in this register is the CIC5
decimation rate minus one. This is interpreted as an unsigned
8-bit integer, but due to limited growth in the CIC5 filter accu-
mulators this value should be limited to 31 (decimation = 32).
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