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| 型号： | AD9510BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 1/56页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK DIST 8OUT PLL 64LFCSP |
| 标准包装： | 750 |
| 类型： | 扇出缓冲器（分配），除法器 |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:8 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.2GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
| 配用： | AD9510-VCO/PCBZ-ND - BOARD EVALUATION FOR AD9510 AD9510/PCBZ-ND - BOARD EVALUATION FOR AD9510 |
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1.2 GHz Clock Distribution IC, PLL Core,
Dividers, Delay Adjust, Eight Outputs
Data Sheet
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
2005–2013 Analog Devices, Inc. All rights reserved.
FEATURES
Low phase noise phase-locked loop core
Reference input frequencies to 250 MHz
Programmable dual modulus prescaler
Programmable charge pump (CP) current
Separate CP supply (VCPS) extends tuning range
Two 1.6 GHz, differential clock inputs
8 programmable dividers, 1 to 32, all integers
Phase select for output-to-output coarse delay adjust
4 independent 1.2 GHz LVPECL outputs
Additive output jitter of 225 fs rms
4 independent 800 MHz low voltage differential signaling
(LVDS) or 250 MHz complementary metal oxide conductor
(CMOS) clock outputs
Additive output jitter of 275 fs rms
Fine delay adjust on 2 LVDS/CMOS outputs
Serial control port
Space-saving 64-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, and
mixed-signal front ends (MxFEs)
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The AD9510 provides a multi-output clock distribution function
along with an on-chip phase-locked loop (PLL) core. The design
emphasizes low jitter and phase noise to maximize data converter
performance. Other applications with demanding phase noise
and jitter requirements also benefit from this device.
The PLL section consists of a programmable reference divider
(R); a low noise, phase frequency detector (PFD); a precision
charge pump (CP); and a programmable feedback divider (N).
By connecting an external voltage-controlled crystal oscillator
(VCXO) or voltage-controlled oscillator (VCO) to the CLK2
and CLK2B pins, frequencies of up to 1.6 GHz can be synchronized
to the input reference.
There are eight independent clock outputs. Four outputs are low
voltage positive emitter-coupled logic (LVPECL) at 1.2 GHz,
and four are selectable as either LVDS (800 MHz) or CMOS
(250 MHz) levels.
Each output has a programmable divider that can be bypassed
or set to divide by any integer up to 32. The phase of one clock
output relative to another clock output can be varied by means
of a divider phase select function that serves as a coarse timing
adjustment. Two of the LVDS/CMOS outputs feature program-
mable delay elements with full-scale ranges up to 8 ns of delay.
This fine tuning delay block has 5-bit resolution, giving 25
possible delays from which to choose for each full-scale setting
(Register 0x36 and Register 0x3A = 00000b to 11000b).
The AD9510 is ideally suited for data converter clocking
applications where maximum converter performance is
achieved by encode signals with subpicosecond jitter.
The AD9510 is available in a 64-lead LFCSP and can be operated
from a single 3.3 V supply. An external VCO, which requires an
extended voltage range, can be accommodated by connecting
the charge pump supply (VCP) to 5.5 V. The temperature range
is 40°C to +85°C.
05046-001
R DIVIDER
N DIVIDER
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
PLL
SETTINGS
CLK2
STATUS
CLK2B
PROGRAMMABLE
DIVIDERS AND
PHASE ADJUST
OUT7
OUT7B
LVDS/CMOS
/1, /2, /3... /31, /32
OUT6
OUT6B
LVDS/CMOS
/1, /2, /3... /31, /32
OUT0
OUT0B
LVPECL
/1, /2, /3... /31, /32
OUT1
OUT1B
LVPECL
/1, /2, /3... /31, /32
OUT2
OUT2B
LVPECL
/1, /2, /3... /31, /32
OUT3
OUT3B
LVPECL
/1, /2, /3... /31, /32
OUT4
OUT4B
LVDS/CMOS
/1, /2, /3... /31, /32
OUT5
OUT5B
LVDS/CMOS
/1, /2, /3... /31, /32
T
CLK1
CLK1B
REFIN
REFINB
FUNCTION
SCLK
SDIO
SDO
CSB
SERIAL
CONTROL
PORT
CP
CPRSET
DISTRIBUTION
REF
SYNCB,
RESETB
PDB
RSET
AD9510
GND
VS
VCP
PLL
REF
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| AD9511BCPZ-REEL7 | IC CLOCK DIST 5OUT PLL 48LFCSP |
| AD9512UCPZ-EP-R7 | IC CLOCK DIST 5OUT PLL 48LFCSP |
| AD9512UCPZ-EP | IC CLOCK DIST 5OUT PLL 48LFCSP |
| AD9513BCPZ-REEL7 | IC CLOCK DIST 3OUT PLL 32LFCSP |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9510-VCO/PCB | 制造商:Analog Devices 功能描述:EVAL BD FOR 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE, DIVIDER - Bulk 制造商:Analog Devices 功能描述:IC ((NS)) |
| AD9510-VCO/PCBZ | 功能描述:BOARD EVALUATION FOR AD9510 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9511 | 制造商:AD 制造商全称:Analog Devices 功能描述:1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
| AD9511/PCB | 制造商:Analog Devices 功能描述:1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,DIVIDERS, DELAY ADJUST, FIVE OUTPUTS 制造商:Analog Devices 功能描述:EVAL BD FOR AD9511 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,D - Bulk |
| AD9511BCPZ | 功能描述:IC CLOCK DIST 5OUT PLL 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
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