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| 型号： | AD9510BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 32/56页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK DIST 8OUT PLL 64LFCSP |
| 标准包装： | 750 |
| 类型： | 扇出缓冲器（分配），除法器 |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:8 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.2GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
| 配用： | AD9510-VCO/PCBZ-ND - BOARD EVALUATION FOR AD9510 AD9510/PCBZ-ND - BOARD EVALUATION FOR AD9510 |
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AD9510
Data Sheet
Rev. B | Page 38 of 56
POWER-DOWN MODES
Chip Power-Down or Sleep Mode—PDB
The PDB chip power-down turns off most of the functions and
currents in the AD9510. When the PDB mode is enabled, a chip
power-down is activated by taking the FUNCTION pin to a logic
low level. The chip remains in this power-down state until PDB
is brought back to logic high. When woken up, the AD9510 returns
to the settings programmed into its registers prior to the power-
down, unless the registers are changed by new programming
while the PDB mode is active.
The PDB power-down mode shuts down the currents on the
chip, except the bias current necessary to maintain the LVPECL
outputs in a safe shutdown mode. This is needed to protect the
LVPECL output circuitry from damage that can be caused by
certain termination and load configurations when tristated.
Because this is not a complete power-down, it is also called
sleep mode.
When the AD9510 is in a PDB power-down or sleep mode, the
chip is in the following state:
The PLL is off (asynchronous power-down).
All clocks and sync circuits are off.
All dividers are off.
All LVDS/CMOS outputs are off.
All LVPECL outputs are in safe off mode.
The serial control port is active, and the chip responds to
commands.
If the AD9510 clock outputs must be synchronized to each
other, a SYNC (see the Single-Chip Synchronization section) is
required upon exiting power-down mode.
PLL Power-Down
The PLL section of the AD9510 can be selectively powered
down. There are three PLL power-down modes, set by the
values in Register 0x0A[1:0], as shown in Table 20.
Table 20. Register 0x0A: PLL Power-Down
[1]
[0]
Mode
0
Normal Operation
0
1
Asynchronous Power-Down
1
0
Normal Operation
1
Synchronous Power-Down
In asynchronous power-down mode, the device powers down
as soon as the registers are updated.
In synchronous power-down mode, the PLL power-down is
gated by the charge pump to prevent unwanted frequency
jumps. The device goes into power-down on the occurrence of
the next charge pump event after the registers are updated.
Distribution Power-Down
The distribution section can be powered down by writing to
Register 0x58[3] = 1. This turns off the bias to the distribution
section. If the LVPECL power-down mode is normal operation
[00], it is possible for a low impedance load on that LVPECL
output to draw significant current during this power-down. If
the LVPECL power-down mode is set to [11], the LVPECL
output is not protected from reverse bias and can be damaged
under certain termination conditions.
When combined with the PLL power-down, this mode results in
the lowest possible power-down current for the AD9510.
Individual Clock Output Power-Down
Any of the eight clock distribution outputs can be powered down
individually by writing to the appropriate registers via the SCP.
The register map details the individual power-down settings for
each output. The LVDS/CMOS outputs can be powered down,
regardless of their output load configuration.
The LVPECL outputs have multiple power-down modes (see
Register Address 3C, Register Address 3D, Register Address 3E,
and Register Address 3F in Table 25). These give some flexibility in
dealing with various output termination conditions. When the
mode is set to [10], the LVPECL output is protected from reverse
bias to 2 VBE + 1 V. If the mode is set to [11], the LVPECL output
is not protected from reverse bias and can be damaged under
certain termination conditions. This setting also affects the
operation when the distribution block is powered down with
Register 0x58[3] = 1b (see the Distribution Power-Down section).
Individual Circuit Block Power-Down
Many of the AD9510 circuit blocks (CLK1, CLK2, REFIN, and
so on) can be powered down individually. This gives flexibility
in configuring the part for power savings whenever certain chip
functions are not needed.
RESET MODES
The AD9510 has several ways to force the chip into a reset
condition.
Power-On Reset—Start-Up Conditions when VS is
Applied
A power-on reset (POR) is issued when the VS power supply is
turned on. This initializes the chip to the power-on conditions
that are determined by the default register settings. These are
indicated in the default value column of Table 24.
Asynchronous Reset via the FUNCTION Pin
As mentioned in the FUNCTION Pin section, a hard reset,
RESETB: Register 0x58[6:5] = 00b (Default), restores the chip
to the default settings.
Soft Reset via the Serial Port
The serial control port allows a soft reset by writing to
Register 0x00[5] = 1b. When this bit is set, the chip executes
a soft reset. This restores the default values to the internal
registers, except for Register 0x00 itself.
This bit is not self-clearing. The bit must be written to
Register 0x00[5] = 0b in order for the operation of the part
to continue.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9510-VCO/PCB | 制造商:Analog Devices 功能描述:EVAL BD FOR 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE, DIVIDER - Bulk 制造商:Analog Devices 功能描述:IC ((NS)) |
| AD9510-VCO/PCBZ | 功能描述:BOARD EVALUATION FOR AD9510 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9511 | 制造商:AD 制造商全称:Analog Devices 功能描述:1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
| AD9511/PCB | 制造商:Analog Devices 功能描述:1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,DIVIDERS, DELAY ADJUST, FIVE OUTPUTS 制造商:Analog Devices 功能描述:EVAL BD FOR AD9511 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,D - Bulk |
| AD9511BCPZ | 功能描述:IC CLOCK DIST 5OUT PLL 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
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