- 您现在的位置：买卖IC网 > PDF目录1986 > AD9510BCPZ-REEL7 (Analog Devices Inc)IC CLOCK DIST 8OUT PLL 64LFCSP PDF资料下载
参数资料
| 型号： | AD9510BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 26/56页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK DIST 8OUT PLL 64LFCSP |
| 标准包装： | 750 |
| 类型： | 扇出缓冲器（分配），除法器 |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:8 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.2GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
| 配用： | AD9510-VCO/PCBZ-ND - BOARD EVALUATION FOR AD9510 AD9510/PCBZ-ND - BOARD EVALUATION FOR AD9510 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页当前第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页
AD9510
Data Sheet
Rev. B | Page 32 of 56
FUNCTION PIN
The FUNCTION pin (16) has three functions that are selected
by the value in Register 0x58[6:5]. This pin is internally pulled
down by a 30 k resistor. If this pin is left unconnected, the
part is in reset by default. To avoid this, connect this pin to VS
with a 1 k resistor.
RESETB: Register 0x58[6:5] = 00b (Default)
In its default mode, the FUNCTION pin acts as RESETB, which
generates an asynchronous reset or hard reset when pulled low.
The resulting reset writes the default values into the serial control
port buffer registers as well as loading them into the chip control
registers. When the RESETB signal goes high again, a synchro-
nous sync is issued (see the SYNCB: Register 0x58[6:5] = 01b
section) and the AD9510 resumes operation according to the
default values of the registers.
SYNCB: Register 0x58[6:5] = 01b
Using the FUNCTION pin causes a synchronization or
alignment of phase among the various clock outputs. The
synchronization applies only to clock outputs that
Are not powered down
The divider is not masked (no sync = 0b)
Are not bypassed (bypass = 0b)
SYNCB is level and rising edge sensitive. When SYNCB is low,
the set of affected outputs are held in a predetermined state,
defined by the start high bit of each divider. On a rising edge,
the dividers begin after a predefined number of fast clock cycles
(fast clock is the selected clock input, CLK1 or CLK2) as
determined by the values in the phase offset bits of the divider.
The SYNCB application of the FUNCTION pin is always active,
regardless of whether the pin is also assigned to perform reset
or power-down. When the SYNCB function is selected, the
FUNCTION pin does not act as either RESETB or PDB.
PDB: Register 0x58[6:5] = 11b
The FUNCTION pin can also be programmed to work as an
asynchronous full power-down, PDB. Even in this full power-
down mode, there is still some residual VS current because
some on-chip references continue to operate. In PDB mode,
the FUNCTION pin is active low. The chip remains in a power-
down state until PDB is returned to logic high. The chip returns
to the settings programmed prior to the power-down.
See the Chip Power-Down or Sleep Mode—PDB section for more
details on what occurs during a PDB initiated power-down.
DISTRIBUTION SECTION
As previously mentioned, the AD9510 is partitioned into two
operational sections: PLL and distribution. The PLL Section is
discussed previously in this data sheet. If desired, the distribution
section can be used separately from the PLL section.
CLK1 AND CLK2 CLOCK INPUTS
Either CLK1 or CLK2 can be selected as the input to the distri-
bution section. The CLK1 input can be connected to drive the
distribution section only. CLK1 is selected as the source for the
distribution section by setting Register 0x45[0] = 1. This is the
power-up default state.
CLK1 and CLK2 work for inputs up to 1600 MHz. A higher input
slew rate improves the jitter performance. The input level must
be between approximately 150 mV p-p to no more than 2 V p-p.
Anything greater may result in turning on the protection diodes
on the input pins, which may degrade the jitter performance.
See Figure 35 for the CLK1 and CLK2 equivalent input circuit.
These inputs are fully differential and self-biased. The signal
must be ac-coupled using capacitors. If a single-ended input
must be used, this can be accommodated by ac-coupling to one
side of the differential input only. Bypass the other side of the
input to a quiet ac ground by a capacitor.
Power down the unselected clock input (CLK1 or CLK2) to
eliminate any possibility of unwanted crosstalk between the
selected clock input and the unselected clock input.
DIVIDERS
Each of the eight clock outputs of the AD9510 has its own
divider. The divider can be bypassed to obtain an output at the
same frequency as the input (1×). When a divider is bypassed,
it is powered down to save power.
All integer divide ratios from 1 to 32 can be selected. A divide
ratio of 1 is selected by bypassing the divider.
Each divider can be configured for divide ratio, phase, and duty
cycle. The phase and duty cycle values that can be selected
depend on the divide ratio that is chosen.
Setting the Divide Ratio
The divide ratio is determined by the values written via the serial
control port (SCP) to the registers that control each individual
output, OUT0 to OUT7. These are the even numbered registers
beginning at Register 0x48 and going through Register 0x56.
Each of these registers is divided into bits that control the
number of clock cycles that the divider output stays high
(HIGH_CYCLES[3:0]) and the number of clock cycles that the
divider output stays low (LOW_CYCLES[7:4]). Each value is 4
bits and has the range of 0 to 15.
The divide ratio is set by
Divide Ratio = (HIGH_CYCLES + 1) + (LOW_CYCLES + 1)
相关PDF资料 |
PDF描述 |
|---|---|
| AD9511BCPZ-REEL7 | IC CLOCK DIST 5OUT PLL 48LFCSP |
| AD9512UCPZ-EP-R7 | IC CLOCK DIST 5OUT PLL 48LFCSP |
| AD9512UCPZ-EP | IC CLOCK DIST 5OUT PLL 48LFCSP |
| AD9513BCPZ-REEL7 | IC CLOCK DIST 3OUT PLL 32LFCSP |
| AD9514BCPZ-REEL7 | IC CLOCK DIST 3OUT PLL 32LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9510-VCO/PCB | 制造商:Analog Devices 功能描述:EVAL BD FOR 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE, DIVIDER - Bulk 制造商:Analog Devices 功能描述:IC ((NS)) |
| AD9510-VCO/PCBZ | 功能描述:BOARD EVALUATION FOR AD9510 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9511 | 制造商:AD 制造商全称:Analog Devices 功能描述:1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
| AD9511/PCB | 制造商:Analog Devices 功能描述:1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,DIVIDERS, DELAY ADJUST, FIVE OUTPUTS 制造商:Analog Devices 功能描述:EVAL BD FOR AD9511 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,D - Bulk |
| AD9511BCPZ | 功能描述:IC CLOCK DIST 5OUT PLL 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
发布紧急采购，3分钟左右您将得到回复。