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| 型号： | AD9510BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 50/56页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK DIST 8OUT PLL 64LFCSP |
| 标准包装： | 750 |
| 类型： | 扇出缓冲器（分配），除法器 |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:8 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.2GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
| 配用： | AD9510-VCO/PCBZ-ND - BOARD EVALUATION FOR AD9510 AD9510/PCBZ-ND - BOARD EVALUATION FOR AD9510 |
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AD9510
Data Sheet
Rev. B | Page 54 of 56
APPLICATIONS INFORMATION
USING THE AD9510 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. An ADC can be thought of
as a sampling mixer; any noise, distortion, or timing jitter on
the clock is combined with the desired signal at the analog-to-
digital output. Clock integrity requirements scale with the analog
input frequency and resolution, with higher analog input fre-
quency applications at ≥ 14-bit resolution being the most
stringent. The theoretical SNR of an ADC is limited by the
ADC resolution and the jitter on the sampling clock. Considering
an ideal ADC of infinite resolution where the step size and
quantization error can be ignored, the available SNR can be
expressed approximately by
×
=
j
ft
SNR
2π
1
log
20
where:
f is the highest analog frequency being digitized.
tj is the rms jitter on the sampling clock.
Figure 53 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
Figure 53. ENOB and SNR vs. Analog Input Frequency
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection, which can
provide superior clock performance in a noisy environment.)
The AD9510 features both LVPECL and LVDS outputs that
provide differential clock outputs, which enable clock solutions
that maximize converter SNR performance. Consider the input
requirements of the ADC (differential or single-ended, logic
level, termination) when selecting the best clocking/converter
solution.
CMOS CLOCK DISTRIBUTION
The AD9510 provides four clock outputs (OUT4 to OUT7),
which are selectable as either CMOS or LVDS levels. When
selected as CMOS, these outputs provide for driving devices
requiring CMOS level logic at their clock inputs.
Whenever single-ended CMOS clocking is used, follow some of
the following general guidelines.
Point-to-point nets must be designed such that a driver has one
receiver only on the net, if possible. This allows for simple termina-
tion schemes and minimizes ringing due to possible mismatched
impedances on the net. Series termination at the source is generally
required to provide transmission line matching and/or to reduce
current transients at the driver. The value of the resistor is
dependent on the board design and timing requirements (typically
10 to 100 is used). CMOS outputs are limited in terms of
the capacitive load or trace length that they can drive. Typically,
trace lengths less than 3 inches are recommended to preserve
signal rise/fall times and preserve signal integrity.
Figure 54. Series Termination of CMOS Output
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the AD9510 do not supply enough current
to provide a full voltage swing with a low impedance resistive,
far-end termination, as shown in Figure 55. The far-end termi-
nation network must match the PCB trace impedance and provide
the desired switching point. The reduced signal swing may still
meet receiver input requirements in some applications. This can
be useful when driving long trace lengths on less critical nets.
Figure 55. CMOS Output with Far-End Termination
120
100
80
60
40
20
4
6
8
10
12
14
16
18
1
3
10
30
100
05046-024
FULL-SCALE SINE WAVE ANALOG INPUT FREQUENCY (MHz)
SNR
(dB)
ENOB
tj = 50fs
tj = 0.1ps
tj = 1ps
tj = 10ps
tj = 100ps
tj = 1ns
SNR = 20log10
1
2
πftj
05046-025
10
MICROSTRIP
GND
5pF
60.4
1.0 INCH
CMOS
05046-027
50
10
OUT4, OUT5, OUT6, OUT7
SELECTED AS CMOS
VPULLUP = 3.3V
CMOS
3pF
100
100
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9510-VCO/PCB | 制造商:Analog Devices 功能描述:EVAL BD FOR 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE, DIVIDER - Bulk 制造商:Analog Devices 功能描述:IC ((NS)) |
| AD9510-VCO/PCBZ | 功能描述:BOARD EVALUATION FOR AD9510 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9511 | 制造商:AD 制造商全称:Analog Devices 功能描述:1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
| AD9511/PCB | 制造商:Analog Devices 功能描述:1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,DIVIDERS, DELAY ADJUST, FIVE OUTPUTS 制造商:Analog Devices 功能描述:EVAL BD FOR AD9511 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,D - Bulk |
| AD9511BCPZ | 功能描述:IC CLOCK DIST 5OUT PLL 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
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