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| 型号： | AD9510BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 22/56页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK DIST 8OUT PLL 64LFCSP |
| 标准包装： | 750 |
| 类型： | 扇出缓冲器（分配），除法器 |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:8 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.2GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
| 配用： | AD9510-VCO/PCBZ-ND - BOARD EVALUATION FOR AD9510 AD9510/PCBZ-ND - BOARD EVALUATION FOR AD9510 |
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Data Sheet
AD9510
Rev. B | Page 29 of 56
VCO/VCXO Feedback Divider—N (P, A, B)
The N divider is a combination of a prescaler, P (3 bits), and two
counters, A (6 bits) and B (13 bits). Although the PLL of the
prescaler that allows lower values of N. The prescaler has both
a dual modulus (DM) and a fixed divide (FD) mode. The AD9510
prescaler modes are shown in Table 15.
Table 15. PLL Prescaler Modes
Mode
(FD = Fixed Divide,
DM = Dual Modulus)
Value in
Register 0x0A[4:2]
Divide By
FD
000
1
FD
001
2
P = 2 DM
010
P/P + 1 = 2/3
P = 4 DM
011
P/P + 1 = 4/5
P = 8 DM
100
P/P + 1 = 8/9
P = 16 DM
101
P/P + 1 = 16/17
P = 32 DM
110
P/P + 1 = 32/33
FD
111
3
When using the prescaler in FD mode, the A counter is not
used, and the B counter may need to be bypassed. The DM
prescaler modes set some upper limits on the frequency, which
can be applied to CLK2. See Table 16.
Table 16. Frequency Limits of Each Prescaler Mode
A and B Counters
The AD9510 B counter has a bypass mode (B = 1), which is not
available on the ADF4106. The B counter bypass mode is valid
only when using the prescaler in FD mode. The B counter is
bypassed by writing 1 to the B counter bypass bit (Register 0x0A[6]
= 1b). The valid range of the B counter is 3 to 8191. The default
after a reset is 0, which is invalid.
Note that the A counter is not used when the prescaler is in
FD mode.
Note also that the A/B counters have their own reset bit, which
is primarily intended for testing. The A and B counters can also
be reset using the shared reset bit of the R, A, and B counters
(Register 0x09[0]).
Determining Values for P, A, B, and R
When operating the AD9510 in a dual-modulus mode, the
input reference frequency, fREF, is related to the VCO output
frequency, fVCO.
fVCO = (fREF/R) × (PB + A) = fREF × N/R
When operating the prescaler in fixed divide mode, the A
counter is not used and the equation simplifies to
fVCO = (fREF/R) × (PB) = fREF × N/R
By using combinations of dual modulus and fixed divide modes,
the AD9510 can achieve values of N all the way down to N = 1.
Table 17 shows how a 10 MHz reference input can be locked to
any integer multiple of N. Note that the same value of N can be
derived in different ways, as illustrated by N = 12.
Table 17. P, A, B, R—Smallest Values for N
fREF
R
P
A
B
N
fVCO
Mode
Notes
10
1
X
1
10
FD
P = 1, B = 1 (Bypassed)
10
1
2
X
1
2
20
FD
P = 2, B = 1 (Bypassed)
10
1
X
3
30
FD
P = 1, B = 3
10
1
X
4
40
FD
P = 1, B = 4
10
1
X
5
50
FD
P = 1, B = 5
10
1
2
X
3
6
60
FD
P = 2, B = 3
10
1
2
0
3
6
60
DM
P/P + 1 = 2/3, A = 0, B = 3
10
1
2
1
3
7
70
DM
P/P + 1 = 2/3, A = 1, B = 3
10
1
2
3
8
80
DM
P/P + 1 = 2/3, A = 2, B = 3
10
1
2
1
4
9
90
DM
P/P + 1 = 2/3, A = 1, B = 4
10
1
2
X
5
10
100
FD
P = 2, B = 5
10
1
2
0
5
10
100
DM
P/P + 1 = 2/3, A = 0, B = 5
10
1
2
1
5
11
110
DM
P/P + 1 = 2/3, A = 1, B = 5
10
1
2
X
6
12
120
FD
P = 2, B = 6
10
1
2
0
6
12
120
DM
P/P + 1 = 2/3, A = 0, B = 6
10
1
4
0
3
12
120
DM
P/P + 1 = 4/5, A = 0, B = 3
10
1
4
1
3
13
130
DM
P/P + 1 = 4/5, A = 1, B = 3
Mode (DM = Dual Modulus)
CLK2
P = 2 DM (2/3)
<600 MHz
P = 4 DM (4/5)
<1000 MHz
P = 8 DM (8/9)
<1600 MHz
P = 16 DM
<1600 MHz
P = 32 DM
<1600 MHz
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