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| 型号： | AD9511BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 25/60页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK DIST 5OUT PLL 48LFCSP |
| 标准包装： | 750 |
| 类型： | 扇出缓冲器（分配），除法器 |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:5 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.2GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 带卷 (TR) |
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AD9511
Rev. A | Page 31 of 60
Phase Frequency Detector (PFD) and Charge Pump
The PFD takes inputs from the R counter and the N counter
(N = BP + A) and produces an output proportional to the phase
and frequency difference between them. Figure 36 is a
simplified schematic. The PFD includes a programmable delay
element that controls the width of the antibacklash pulse. This
pulse ensures that there is no dead zone in the PFD transfer
function and minimizes phase noise and reference spurs. Two
bits in Register 0Dh <1:0> control the width of the pulse.
05286-
014
D1
Q1
U1
CLR1
R DIVIDER
HI
UP
D2
Q2
U2
CLR2
N DIVIDER
HI
DOWN
CP
CHARGE
PUMP
VP
GND
U3
PROGRAMMABLE
DELAY
ANTIBACKLASH
PULSE WIDTH
Figure 36. PFD Simplified Schematic and Timing (In Lock)
Antibacklash Pulse
The PLL features a programmable antibacklash pulse width that
is set by the value in Register 0Dh<1:0>. The default
antibacklash pulse width is 1.3 ns (0Dh<1:0> = 00b) and
normally should not need to be changed. The antibacklash
pulse eliminates the dead zone around the phase-locked
condition and thereby reduces the potential for certain spurs
that could be impressed on the VCO signal.
STATUS Pin
The output multiplexer on the AD9511 allows access to various
signals and internal points on the chip at the STATUS pin.
Figure 37 shows a block diagram of the STATUS pin section.
The function of the STATUS pin is controlled by Register
08h<5:2>.
PLL Digital Lock Detect
The STATUS pin can display two types of PLL lock detect:
digital (DLD) and analog (ALD). Whenever digital lock detect
is desired, the STATUS pin provides a CMOS level signal, which
can be active high or active low.
The digital lock detect has one of two time windows, as selected
by Register 0Dh<5>. The default (ODh<5> = 0b) requires the
signal edges on the inputs to the PFD to be coincident within
9.5 ns to set the DLD true, which then must separate by at least
15 ns to give DLD = false.
The other setting (ODh<5> = 1b) makes these coincidence
times 3.5 ns for DLD = true and 7 ns for DLD = false.
The DLD may be disabled by writing 1 to Register 0Dh<6>.
If the signal at REFIN goes away while DLD is true, the DLD
will not necessarily indicate loss-of-lock. See the Loss of
Reference section for more information.
0
5286-
015
OFF (LOW) (DEFAULT)
DIGITAL LOCK DETECT (ACTIVE HIGH)
N DIVIDER OUTPUT
DIGITAL LOCK DETECT (ACTIVE LOW)
R DIVIDER OUTPUT
ANALOG LOCK DETECT (N-CHANNEL OPEN DRAIN)
A COUNTER OUTPUT
PRESCALER OUTPUT (NCLK)
PFD UP PULSE
PFD DOWN PULSE
LOSS OF REFERENCE (ACTIVE HIGH)
TRI-STATE
ANALOG LOCK DETECT (P-CHANNEL OPEN DRAIN)
LOSS OF REFERENCE OR LOCK DETECT (ACTIVE HIGH)
LOSS OF REFERENCE OR LOCK DETECT (ACTIVE LOW)
LOSS OF REFERENCE (ACTIVE LOW)
PLL MUX CONTROL
08h <5:2>
SYNC DETECT ENABLE
58h <0>
SYNC
DETECT
CONTROL
FOR
ANALOG
LOCK
DETECT
MODE
VS
GND
STATUS
PIN
Figure 37. STATUS Pin Circuit CLK1 Clock Input
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9511-VCO/PCB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9511 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,D - Bulk |
| AD9512 | 制造商:AD 制造商全称:Analog Devices 功能描述:800 MHz Clock Distribution IC,1.5 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
| AD9512/PCB | 制造商:Analog Devices 功能描述:Evaluation Kit For 1.2 GHZ Clock Distribution IC, 1.6 GHZ Inputs, Dividers, Delay Adjust, Five Outputs 制造商:Analog Devices 功能描述:EVAL KIT FOR 1.2 GHZ CLOCK DISTRIBUTION IC, 1.6 GHZ INPUTS, - Bulk |
| AD9512/PCBZ | 功能描述:BOARD EVAL FOR AD9512 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9512BCPZ | 功能描述:IC CLOCK DIST 5OUT PLL 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
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