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| 型号： | AD9511BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 26/60页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK DIST 5OUT PLL 48LFCSP |
| 标准包装： | 750 |
| 类型： | 扇出缓冲器（分配），除法器 |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:5 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.2GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 带卷 (TR) |
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AD9511
Rev. A | Page 32 of 60
PLL Analog Lock Detect
An analog lock detect (ALD) signal may be selected. When
ALD is selected, the signal at the STATUS pin is either an open-
drain P-channel (08h<5:2> = 1100b) or an open-drain N-
channel (08h<5:2> = 0101b).
The analog lock detect signal is true (relative to the selected
mode) with brief false pulses. These false pulses get shorter as
the inputs to the PFD are nearer to coincidence and longer as
they are further from coincidence.
To extract a usable analog lock detect signal, an external RC
network is required to provide an analog filter with the
appropriate RC constant to allow for the discrimination of a
lock condition by an external voltage comparator. A 1 kΩ
resistor in parallel with a small capacitance usually fulfills this
requirement. However, some experimentation may be required
to get the desired operation.
The analog lock detect function may introduce some spurious
energy into the clock outputs. It is prudent to limit the use of
the ALD when the best possible jitter/phase noise performance
is required on the clock outputs.
Loss of Reference
The AD9511 PLL can warn of a loss-of-reference signal at
REFIN. The loss-of-reference monitor internally sets a flag
called LREF. Externally, this signal can be observed in several
ways on the STATUS pin, depending on the PLL MUX control
settings in Register 08h<5:2>. The LREF alone can be observed
as an active high signal by setting 08h<5:2> = <1010b> or as an
active low signal by setting 08h<5:2> = <1111b>.
The loss-of-reference circuit is clocked by the signal from the
VCO, which means that there must be a VCO signal present to
detect a loss of reference.
The digital lock detect (DLD) block of the AD9511 requires a
PLL reference signal to be present for the digital lock detect
output to be valid. It is possible to have a digital lock detect
indication (DLD = true) that remains true even after a loss-of-
reference signal. For this reason, the digital lock detect signal
alone cannot be relied upon if the reference has been lost. There
is a way to combine the DLD and the LREF into a single signal
at the STATUS pin. Set 08h<5:2> = <1101b> to get a signal that
is the logical OR of the loss-of-lock (inverse of DLD) and the
loss-of-reference (LREF) active high. If an active low version of
this same signal is desired, set 08h<5:2> = <1110b>.
The reference monitor is enabled only after the DLD signal has
been high for the number of PFD cycles set by the value in
07h<6:5>. This delay is measured in PFD cycles. The delay
ranges from 3 PFD cycles (default) to 24 PFD cycles. When the
reference goes away, LREF goes true and the charge pump goes
into tri-state.
User intervention is required to take the part out of this state.
First, 07h<2> = 0b must be written in order to disable the loss-
of-reference circuit, taking the charge pump out of tri-state and
causing LREF to go false. A second write of 07h<2> = 1b is
required to re-enable the loss-of-reference circuit.
0
5
286
-0
34
PLL LOOP LOCKS
DLD GOES TRUE
LREF IS FALSE
CHECK FOR PRESENCE
OF REFERENCE.
LREF STAYS FALSE IF
REFERENCE IS DETECTED.
CHARGE PUMP
GOES INTO TRI-STATE.
LREF SET TRUE.
MISSING
REFERENCE
DETECTED
n PFD CYCLES WITH
DLD TRUE
(n SET BY 07h<6:5>)
WRITE 07h<2> = 0
LREF SET FALSE
CHARGE PUMP COMES
OUT OF TRI-STATE
WRITE 07h<2> = 1
LOR ENABLED
Figure 38. Loss of Reference Sequence of Events
FUNCTION PIN
The FUNCTION pin (12) has three functions that are selected
by the value in Register 58h<6:5>. This pin is internally pulled
down by a 30 kΩ resistor. If this pin is left NC, the part is in
reset by default. To avoid this, connect this pin to VS with a
1 kΩ resistor.
RESETB: 58h<6:5> = 00b (Default)
In its default mode, the FUNCTION pin acts as RESETB, which
generates an asynchronous reset or hard reset when pulled low.
The resulting reset writes the default values into the serial
control port buffer registers as well as loading them into the
chip control registers. When the RESETB signal goes high
again, a synchronous sync is issued (see the SYNCB: 58h<6:5>
= 01b section) and the AD9511 resumes operation according to
the default values of the registers.
SYNCB: 58h<6:5> = 01b
The FUNCTION pin may be used to cause a synchronization or
alignment of phase among the various clock outputs. The
synchronization applies only to clock outputs that:
are not powered down
the divider is not masked (no sync = 0b)
are not bypassed (bypass = 0b)
SYNCB is level and rising edge sensitive. When SYNCB is low,
the set of affected outputs are held in a predetermined state,
defined by each divider’s start high bit. On a rising edge, the
dividers begin after a predefined number of fast clock cycles
(fast clock is the selected clock input, CLK1 or CLK2) as
determined by the values in the divider’s phase offset bits.
The SYNCB application of the FUNCTION pin is always active,
regardless of whether the pin is also assigned to perform reset
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9511-VCO/PCB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9511 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,D - Bulk |
| AD9512 | 制造商:AD 制造商全称:Analog Devices 功能描述:800 MHz Clock Distribution IC,1.5 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
| AD9512/PCB | 制造商:Analog Devices 功能描述:Evaluation Kit For 1.2 GHZ Clock Distribution IC, 1.6 GHZ Inputs, Dividers, Delay Adjust, Five Outputs 制造商:Analog Devices 功能描述:EVAL KIT FOR 1.2 GHZ CLOCK DISTRIBUTION IC, 1.6 GHZ INPUTS, - Bulk |
| AD9512/PCBZ | 功能描述:BOARD EVAL FOR AD9512 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9512BCPZ | 功能描述:IC CLOCK DIST 5OUT PLL 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
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