- 您现在的位置：买卖IC网 > PDF目录1986 > AD9511BCPZ-REEL7 (Analog Devices Inc)IC CLOCK DIST 5OUT PLL 48LFCSP PDF资料下载
参数资料
| 型号： | AD9511BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 33/60页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK DIST 5OUT PLL 48LFCSP |
| 标准包装： | 750 |
| 类型： | 扇出缓冲器（分配），除法器 |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:5 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.2GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页当前第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页
AD9511
Rev. A | Page 39 of 60
05286-
038
3.5mA
OUT
OUTB
Figure 42. LVDS Output Simplified Equivalent Circuit
POWER-DOWN MODES
Chip Power-Down or Sleep Mode—PDB
The PDB chip power-down turns off most of the functions and
currents in the AD9511. When the PDB mode is enabled, a chip
power-down is activated by taking the FUNCTION pin to a
logic low level. The chip remains in this power-down state until
PDB is brought back to logic high. When woken up, the
AD9511 returns to the settings programmed into its registers
prior to the power-down, unless the registers are changed by
new programming while the PDB mode is active.
The PDB power-down mode shuts down the currents on the
chip, except the bias current necessary to maintain the LVPECL
outputs in a safe shutdown mode. This is needed to protect the
LVPECL output circuitry from damage that could be caused by
certain termination and load configurations when tri-stated.
Because this is not a complete power-down, it can be called
sleep mode.
When the AD9511 is in a PDB power-down or sleep mode, the
chip is in the following state:
The PLL is off (asynchronous power-down).
All clocks and sync circuits are off.
All dividers are off.
All LVDS/CMOS outputs are off.
All LVPECL outputs are in safe off mode.
The serial control port is active, and the chip responds to
commands.
If the AD9511 clock outputs must be synchronized to each
other, a SYNC (see the Single-Chip Synchronization section) is
required upon exiting power-down mode.
PLL Power-Down
The PLL section of the AD9511 can be selectively powered
down. There are three PLL power-down modes, set by the
values in Register 0Ah<1:0>, as shown in Table 19.
Table 19. Register 0Ah: PLL Power-Down
<1>
<0>
Mode
0
Normal Operation
0
1
Asynchronous Power-Down
1
0
Normal Operation
1
Synchronous Power-Down
In asynchronous power-down mode, the device powers down as
soon as the registers are updated.
In synchronous power-down mode, the PLL power-down is
gated by the charge pump to prevent unwanted frequency
jumps. The device goes into power-down on the occurrence of
the next charge pump event after the registers are updated.
Distribution Power-Down
The distribution section can be powered down by writing to
Register 58h<3> = 1. This turns off the bias to the distribution
section. If the LVPECL power-down mode is normal operation
<00>, it is possible for a low impedance load on that LVPECL
output to draw significant current during this power-down. If
the LVPECL power-down mode is set to <11>, the LVPECL
output is not protected from reverse bias, and can be damaged
under certain termination conditions.
When combined with the PLL power-down, this mode results in
the lowest possible power-down current for the AD9511.
Individual Clock Output Power-Down
Any of the five clock distribution outputs can be powered down
individually by writing to the appropriate registers via the SCP.
The register map details the individual power-down settings for
each output. The LVDS/CMOS outputs may be powered down,
regardless of their output load configuration.
The LVPECL outputs have multiple power-down modes (see
Register 3Dh, Register 3Eh, and Register 3Fh in Table 24).
These give some flexibility in dealing with various output
termination conditions. When the mode is set to <10b>, the
LVPECL output is protected from reverse bias to 2 VBE + 1 V. If
the mode is set to <11b>, the LVPECL output is not protected
from reverse bias and can be damaged under certain
termination conditions. This setting also affects the operation
when the distribution block is powered down with Register
58h<3> = 1b (see the Distribution Power-Down section).
Individual Circuit Block Power-Down
Many of the AD9511 circuit blocks (CLK1, CLK2, and REFIN,
and so on) can be powered down individually. This gives
flexibility in configuring the part for power savings whenever
certain chip functions are not needed.
相关PDF资料 |
PDF描述 |
|---|---|
| AD9512UCPZ-EP-R7 | IC CLOCK DIST 5OUT PLL 48LFCSP |
| AD9512UCPZ-EP | IC CLOCK DIST 5OUT PLL 48LFCSP |
| AD9513BCPZ-REEL7 | IC CLOCK DIST 3OUT PLL 32LFCSP |
| AD9514BCPZ-REEL7 | IC CLOCK DIST 3OUT PLL 32LFCSP |
| AD9515BCPZ-REEL7 | IC CLOCK DIST 2OUT PLL 32LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9511-VCO/PCB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9511 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,D - Bulk |
| AD9512 | 制造商:AD 制造商全称:Analog Devices 功能描述:800 MHz Clock Distribution IC,1.5 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
| AD9512/PCB | 制造商:Analog Devices 功能描述:Evaluation Kit For 1.2 GHZ Clock Distribution IC, 1.6 GHZ Inputs, Dividers, Delay Adjust, Five Outputs 制造商:Analog Devices 功能描述:EVAL KIT FOR 1.2 GHZ CLOCK DISTRIBUTION IC, 1.6 GHZ INPUTS, - Bulk |
| AD9512/PCBZ | 功能描述:BOARD EVAL FOR AD9512 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9512BCPZ | 功能描述:IC CLOCK DIST 5OUT PLL 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
发布紧急采购，3分钟左右您将得到回复。