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参数资料
| 型号： | AD9511BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 50/60页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK DIST 5OUT PLL 48LFCSP |
| 标准包装： | 750 |
| 类型： | 扇出缓冲器（分配），除法器 |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:5 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.2GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 带卷 (TR) |
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AD9511
Rev. A | Page 54 of 60
POWER SUPPLY
The AD9511 requires a 3.3 V ± 5% power supply for VS.
The tables in the Specifications section give the performance
expected from the AD9511 with the power supply voltage
within this range. The absolute maximum range of 0.3 V to
+3.6 V, with respect to GND, must never be exceeded on
the VS pin.
Good engineering practice should be followed in the layout of
power supply traces and ground plane of the PCB. The power
supply should be bypassed on the PCB with adequate
capacitance (>10 μF). The AD9511 should be bypassed with
adequate capacitors (0.1 μF) at all power pins, as close as
possible to the part. The layout of the AD9511 evaluation board
(AD9511/PCB or AD9511-VCO/PCB) is a good example.
The AD9511 is a complex part that is programmed for its
desired operating configuration by on-chip registers. These
registers are not maintained over a shutdown of external power.
This means that the registers can lose their programmed values
if VS is lost long enough for the internal voltages to collapse.
Careful bypassing should protect the part from memory loss
under normal conditions. Nonetheless, it is important that the
VS power supply not become intermittent, or the AD9511 risks
losing its programming.
The internal bias currents of the AD9511 are set by the RSET and
CPRSET resistors. These resistors should be as close as possible to
the values given as conditions in the Specifications section
(RSET = 4.12 kΩ and CPRSET = 5.1 kΩ). These values are standard
1% resistor values and should be readily obtainable. The bias
currents set by these resistors determine the logic levels and
operating conditions of the internal blocks of the AD9511. The
performance figures given in the Specifications section assume
that these resistor values are used.
The VCP pin is the supply pin for the charge pump (CP). The
voltage at this pin (VCP) may be from VS up to 5.5 V, as required
to match the tuning voltage range of a specific VCO/VCXO.
This voltage must never exceed the absolute maximum of 6 V.
VCP should also never be allowed to be less than 0.3 V below
VS or GND, whichever is lower.
The exposed metal paddle on the AD9511 package is an
electrical connection, as well as a thermal enhancement. For
the device to function properly, the paddle must be properly
attached to ground (GND). The PCB acts as a heat sink for the
AD9511; therefore, this GND connection should provide a
good thermal path to a larger dissipation area, such as a ground
plane on the PCB. See the layout of the AD9511 evaluation
board (AD9511/PCB or AD9511-VCO/PCB) for a good
example.
POWER MANAGEMENT
The power usage of the AD9511 can be managed to use only the
power required for the functions that are being used. Unused
features and circuitry can be powered down to save power. The
following circuit blocks can be powered down, or are powered
down when not selected (see the Register Map and Description
section):
The PLL section can be powered down if not needed.
Any of the dividers are powered down when bypassed—
equivalent to divide-by-one.
The adjustable delay block on OUT4 is powered down
when not selected.
Any output may be powered down. However, LVPECL
outputs have both a safe and an off condition. When the
LVPECL output is terminated, only the safe shutdown
should be used to protect the LVPECL output devices. This
still consumes some power.
The entire distribution section can be powered down when
not needed.
Powering down a functional block does not cause the
programming information for that block (in the registers) to be
lost. This means that blocks can be powered on and off without
otherwise having to reprogram the AD9511. However,
synchronization is lost. A SYNC must be issued to
resynchronize (see the Single-Chip Synchronization section).
相关PDF资料 |
PDF描述 |
|---|---|
| AD9512UCPZ-EP-R7 | IC CLOCK DIST 5OUT PLL 48LFCSP |
| AD9512UCPZ-EP | IC CLOCK DIST 5OUT PLL 48LFCSP |
| AD9513BCPZ-REEL7 | IC CLOCK DIST 3OUT PLL 32LFCSP |
| AD9514BCPZ-REEL7 | IC CLOCK DIST 3OUT PLL 32LFCSP |
| AD9515BCPZ-REEL7 | IC CLOCK DIST 2OUT PLL 32LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9511-VCO/PCB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9511 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,D - Bulk |
| AD9512 | 制造商:AD 制造商全称:Analog Devices 功能描述:800 MHz Clock Distribution IC,1.5 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
| AD9512/PCB | 制造商:Analog Devices 功能描述:Evaluation Kit For 1.2 GHZ Clock Distribution IC, 1.6 GHZ Inputs, Dividers, Delay Adjust, Five Outputs 制造商:Analog Devices 功能描述:EVAL KIT FOR 1.2 GHZ CLOCK DISTRIBUTION IC, 1.6 GHZ INPUTS, - Bulk |
| AD9512/PCBZ | 功能描述:BOARD EVAL FOR AD9512 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9512BCPZ | 功能描述:IC CLOCK DIST 5OUT PLL 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
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