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参数资料
| 型号： | ADP1043AFB100EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/72页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION ADP1043A 100W |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 已用 IC / 零件： | ADP1043A |
| 主要属性： | * |
| 次要属性： | * |
| 已供物品： | 板 |
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ADP1043A
SYNCHRONOUS RECTIFICATION
SR1 and SR2 are recommended for use as the PWM control
signals when using synchronous rectification. These PWM
signals can be set up similarly to the other PWM outputs. The
turn-on of these signals can be programmed in two ways. They
can either be turned on to their full PWM value immediately, or
they can be turned on in a soft start fashion. When turned on
in a soft start, the signals ramp up from zero duty cycle to the
desired duty cycle. The advantage of ramping the SR signals is
to minimize a voltage step that would occur by turning the SR
FETs on completely. The advantage of turning the SR signals
completely on immediately is that they can help to minimize
the voltage transient caused by a load step.
Using Register 0x54[1], the SR soft start can be programmed to
occur just once, the first time that the SR signals are enabled, or
every time that the SR signals are enabled.
When programming the ADP1043A to use SR soft start, ensure
correct operation of this function by setting the falling edge of
SR1 (t 10 ) to a lower value than the rising edge of SR1 (t 9 ) and by
setting the falling edge of SR2 (t 12 ) to a lower value than the
rising edge of SR2 (t 11 ).
The speed of the SR enable is approximately 200 μs. This ensures
that in case of a load step, the SR signals (and any other PWM
outputs that are temporarily disabled) can be turned on quickly
enough to prevent damage to the FETs that they are controlling.
ADAPTIVE DEAD TIME CONTROL
A set of registers called the adaptive dead time (ADT) registers
(Register 0x68 to Register 0x6F) allows the dead time between
PWM edges to be adapted on-the-fly. The ADP1043A uses the
ADT only when the modulation is below the dead time (load
current) threshold (programmed in Register 0x68). The Analog
Devices software GUI allows the user to easily program the
dead time values, and it is recommended that the software be
used for that purpose.
Each individual PWM rising and falling edge (t 1 to t 14 ) can then
be programmed to have a specific dead time offset. This offset
can be positive or negative. The offset is relative to the nominal
edge position. For example, if t 1 has a nominal rising edge of
100 ns and the ADT setting for t 1 is ?15 ns, t 1 moves to 85 ns
when it falls below the adaptive dead time threshold. The dead
times are programmed using Register 0x69 to Register 0x6F.
MODULATION LIMIT
Using the modulation limit register (Register 0x2E), it is possible to
apply a maximum modulation limit and a minimum modulation
limit to any PWM signal, thus limiting the modulation range of
any PWM. These limits are a percentage of the switching period.
If the modulation required is lower than the minimum setting,
pulse skipping can be enabled.
Following is an example of how to use the modulation limit
settings. In this example, the switching cycle period is 4 μs
and modulation on the t 2 edge (falling edge) is enabled. The
nominal position of t 2 is set to 1.6 μs, which is 40% of the 4 μs
period. The modulation high limit is set to (nominal + 50%).
Therefore, the modulation high limit is (40% + 50%) = 90% of
the switching cycle period; 90% of 4 μs = 3.6 μs. The modulation
low limit is set to (nominal ? 35%). Therefore, the modulation
low limit is (40% ? 35%) = 5% of the switching cycle period;
5% of 4 μs = 0.2 μs.
The GUI provided with the ADP1043A is recommended for
evaluating this feature of the ADP1043A (see Figure 15).
Figure 15. Setting Modulation Limits (Modulation Range Shown by Arrows)
OrFET CONTROL (GATE)
The GATE control signal drives an external OrFET. The OrFET
gate control is used to protect against power flow into the power
supply from another supply. This ensures that power flows only
out of the power supply and that the unit can be hot-swapped.
The OrFET circuit can be used only when the ADP1043A is
connected to a sense resistor on the low side. The OrFET circuit
is not guaranteed for operation with high-side current sensing.
The GATE pin is an open-drain, N-channel MOSFET. An
external 2.2 kΩ pull-up resistor is recommended. Its output is
normally high to keep the OrFET turned off. When the start-up
criteria have been achieved, the GATE output is pulled low,
allowing the OrFET to turn on. The OrFET turn-on and turn-
off thresholds can be individually programmed. The GATE
outputs are CMOS levels (0 V to 3.3 V). An external driver is
required to turn the OrFET on or off.
The OrFET can be turned off by three methods:
LIGHT LOAD MODE
Register 0x3B allows the ADP1043A to shut down PWM
outputs under light load conditions. The light load current
threshold can be programmed. Below this current threshold,
?
?
?
Fault flag (any fault flag can be programmed to turn off the
OrFET)
Fast OrFET control circuit
Accurate OrFET control circuit
the SR outputs are disabled. The user can also program any of
the other PWM outputs to shut down below this current thresh-
old. This allows the ADP1043A to be used with an interleaved
two transistor forward topology, incorporating phase shedding
at light load. The light load mode digital filter is also used
during light load mode.
Fast OrFET control looks at the reverse voltage across CS2+
and CS2? and is implemented using an analog comparator
(see Figure 16). If the voltage difference between CS2+ and
CS2? is greater than the fast OrFET threshold programmed
in Register 0x30, the OrFET is turned off.
Rev. 0 | Page 15 of 72
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