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参数资料
| 型号： | ADP1043AFB100EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 44/72页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION ADP1043A 100W |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 已用 IC / 零件： | ADP1043A |
| 主要属性： | * |
| 次要属性： | * |
| 已供物品： | 板 |
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ADP1043A
Table 40. Register 0x2C—PSON/Soft Start Setting
Bits
[7:6]
Name
PS_ON setting
R/W
R/W
Description
These bits determine which signal is used by the ADP1043A as the PS_ON control.
Bit 7
Bit 6
PS_ON Setting
0
0
The ADP1043A is always on.
0
1
Hardware PSON pin is used to enable or disable the power supply.
1
0
Software PS_ON bit (Bit 5) is used to enable or disable the power supply.
1
1
Both software PS_ON bit and hardware PSON pin must be enabled before the
ADP1043A is enabled.
5
PS_ON
R/W
Software PS_ON bit.
0 = power supply off.
1 = power supply on.
[4:3]
2
PS_ON delay
Soft stop enable
R/W
R/W
These bits set the time from when the PS_ON control signal is set to when the soft start begins.
Bit 4
Bit 3
Delay (sec)
0
0
0
0
1
0.5
1
0
1
1
1
2
If the soft stop feature is enabled, a soft stop occurs even if a fault flag causes a shutdown event.
This may cause the ADP1043A to continue switching for longer than desired. The user needs to
consider this factor before enabling the soft stop feature.
1 = soft stop time is the same as the soft start time.
0 = no active discharge time. The ADP1043A shuts down the PWM outputs immediately.
[1:0]
Soft start
R/W
These bits set the soft start ramp time, that is, the amount of time that it takes for the power
supply to reach its nominal value.
Bit 1
0
0
1
1
Table 41. Register 0x2D—Pin Polarit y Setting
Bit 0
0
1
0
1
Ramp Time
360 μs
10 ms
20 ms
40 ms
Bits
[7:4]
Name
PGOOD1 on/off
debounce
R/W
R/W
Description
These bits set the debounce time before the PGOOD1 pin is enabled or disabled. At startup,
PGOOD1 is not enabled until a period of time after the following signals are all within normal
limits: power supply, CS1 fast OCP, CS1 accurate OCP, CS2 accurate OCP, UVP, local OVP, and load
OVP. When PSON is disabled, there is a debounce before PGOOD1 is disabled.
Bit 7
0
0
1
1
Bit 6
0
1
0
1
Bit 5
0
0
1
1
Bit 4
0
1
0
1
Delay Time (ms)
320
200
600
0
3
PGOOD2 flags
R/W
0 = any flag can set the PGOOD2 pin.
1 = any flag that has not been configured to be ignored can set the PGOOD2 pin.
2
1
0
FLAGIN polarity
GATE polarity
PSON polarity
R/W
R/W
R/W
This bit sets the polarity of the FLAGIN input pin: 1 = inverted (low = on).
This bit sets the polarity of the OrFET GATE control pin: 1 = inverted (low = on).
This bit sets the polarity of the PSON input pin: 1 = inverted (low = on).
Rev. 0 | Page 44 of 72
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