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参数资料
| 型号： | ADP1043AFB100EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 26/72页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION ADP1043A 100W |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 已用 IC / 零件： | ADP1043A |
| 主要属性： | * |
| 次要属性： | * |
| 已供物品： | 板 |
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ADP1043A
AC SENSE (ACSNS)
The ACSNS circuit performs multiple monitoring functions.
It determines indirectly whether the primary side input voltage
is present, as well as monitoring whether a switching waveform
is present at the output of the synchronous rectifier stage (or
rectifier diodes). The output of the synchronous rectifier stage
(or rectifier diodes) is connected to this pin through an external
resistor divider network.
The ACSNS circuit within the ADP1043A has a comparator
that checks for a signal of 0.45 V or greater every switching
cycle. For example, if the switching frequency is set to 200 kHz,
the switching cycle is 5 μs. The comparator timeout is therefore
set to 5 μs to match the switching cycle. If the comparator does
not trip during the 5 μs interval, the ACSNS flag is set.
VOLT-SECOND BALANCE
The ADP1043A has a dedicated circuit to maintain volt-second
balance in the main transformer when operating in full-bridge
topology. This means that a dc blocking capacitor is not necessary.
The circuit monitors the dc current flowing in both halves of
the full bridge and stores this information. It compensates the
PWM drive signals to ensure equal current flow in both halves
of the full bridge. The input is through the CS1 pin. Several switch-
ing cycles are required for the circuit to operate effectively. The
volt-second balance places up to 80 ns of modulation on the
Also note that the ADP1043A assumes that the CS1 current
pulse signal that it sees first in each cycle is related to OUTB,
and that the second current pulse signal in each cycle is related
to OUTD. If the first current pulse signal is smaller than the
second, OUTB is increased and OUTD is decreased. If the first
current pulse signal is greater than the second, OUTB is
decreased and OUTD is increased.
LOAD LINE
The ADP1043A can optionally introduce a digital load line into
the power supply. This option is programmed in the load line
impedance register (Register 0x36). This feature can be used for
advanced current sharing techniques. By default, the load line is
disabled. The load line is introduced digitally, and its slope can
be programmed. It works by taking the CS2 current reading and
adjusting the output voltage accordingly. A load line of up to
51.5 mΩ can be chosen. Figure 31 shows the load line results
using the ADP1043A evaluation board. The evaluation board
uses a 10 mΩ R SENSE resistor.
100
99
98
DISABLED
OUTB and OUTD pins.
Note that the compensation of the PWM drive signals is per-
formed on t 4 (OUTB) and t 8 (OUTD) only. Therefore, it is
necessary to use these pins as the modulating PWM signals
for the feature to operate correctly.
97
96
95
SETTING 0
SETTING 1
SETTING 2
SETTING 3
SETTING 4
SETTING 5
SETTING 6
SETTING 7
The SR1 and SR2 rising edges (t 9 and t 11 ) can also be indepen-
dently set to modulate due to the volt-second balance circuit.
The SR1 rising edge (t 9 ) modulates in the same direction as the
0
20
40 60 80
R SENSE VOLTAGE DROP (mV)
Figure 31. Load Line Settings
100
120
OUTB falling edge (t 4 ); the SR2 rising edge (t 11 ) modulates in the
same direction as the OUTD falling edge (t 8 ).
Rev. 0 | Page 26 of 72
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