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参数资料
| 型号： | ADP1043AFB100EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 24/72页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION ADP1043A 100W |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 已用 IC / 零件： | ADP1043A |
| 主要属性： | * |
| 次要属性： | * |
| 已供物品： | 板 |
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ADP1043A
OVERCURRENT PROTECTION (OCP)
The ADP1043A has several OCP functions. CS1 and CS2 have
individual OCP circuits to provide both primary and secondary
side protection.
CS1 has two protection circuits: CS1 fast OCP and CS1 accurate
OCP (see Figure 29). CS1 fast OCP is an analog comparator.
When the voltage at the CS1 pin exceeds the (fixed) 1.2 V thresh-
old, the CS1 fast OCP flag is set. A blanking time can be set to
ignore the current spike at the beginning of the current signal. A
debounce time can be programmed to improve the noise immunity
of the OCP circuit. When the CS1 fast OCP comparator is set,
all PWM outputs are immediately disabled for the remainder of
the switching cycle. They are reenabled at the start of the next
switching cycle. This function can be bypassed if not needed.
V IN
CS1 accurate OCP is used for more precise control of over-
current protection. With CS1 accurate OCP, the reading at
the output of the CS1 ADC (Register 0x13) is compared to a
programmable OCP value. The CS1 accurate OCP value can
be programmed from 0 to 31 decimal using Register 0x22,
Bits[4:0]. If the CS1 reading exceeds the CS1 accurate OCP
value, the CS1 accurate OCP flag is set. The speed of this
decision is 10 ms. The response to the flag is programmable.
CS2 has one OCP protection circuit: CS2 accurate OCP. The read-
ing at the output of the CS2 ADC (Register 0x18) is compared
to a programmable OCP threshold. The CS2 OCP threshold
can be programmed from 0 to 254 decimal using Register 0x26,
Bits[7:0]. If the CS2 reading exceeds the CS2 OCP threshold,
the CS2 accurate OCP flag is set. The speed of this decision is
10 ms. The response to the flag is programmable.
OUTA
OUTB
OUTC
OUTD
CS1
ADC
12
CS1 ACCURATE
OCP SETTING
REG 0x22[4:0]
CS1 ACCURATE OCP FLAG
CS1 FAST
OCP FLAG
FLAGS
SHUTDOWN
OUTA
OUTB
OUTC
1.2V
FAST OCP
COMPARATOR
CS1 FAST
OCP BYPASS
REG 0x27[4]
CS1 FAST OCP
BLANKING
REG 0x22[7:5]
CS1 FAST OCP
DEBOUNCE
REG 0x27[7:6]
CYCLE-BY-CYCLE
SHUTDOWN
PWM
OUTD
SR1
SR2
OUTAUX
FLAGIN
Figure 29. CS1 OCP Detailed Internal Schematic
Rev. 0 | Page 24 of 72
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