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参数资料
| 型号： | ADP1043AFB100EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 65/72页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION ADP1043A 100W |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 已用 IC / 零件： | ADP1043A |
| 主要属性： | * |
| 次要属性： | * |
| 已供物品： | 板 |
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ADP1043A
RESONANT MODE OPERATION
The ADP1043A supports control of a resonant converter.
Resonant converters are an alternative to traditional fixed
frequency converters. They offer high switching frequency,
small size, and high efficiency. Figure 38 illustrates a widely
used series resonant converter.
SYNCHRONOUS RECTIFICATION IN RESONANT
MODE
Control of the synchronous rectifiers in a resonant controller is
a complicated issue. The ADP1043A ACSNS comparator can be
used to control the SR signals. In resonant mode operation, the
Q A
Q C
SR2
SR1 output is driven by the rising edge of the ACSNS comparator,
and the SR2 output is driven by the falling edge of the comparator,
C R
L R
I O
Q D
Q B
I R
SR1
C O
R L
V DS (SR2)
Figure 38. Series Resonant Converter
RESONANT MODE ENABLE
ACSNS
To enable the ADP1043A to control a resonant switching con-
SYNC RECT 1 (SR1)
Δ t 9
Δ t 10
verter, Register 0x40 must be set to a value of 0x3F. In resonant
mode, the PWM outputs have a fixed duty cycle with variable
frequency.
SYNC RECT 2 (SR2)
Δ t 11
Δ t 12
PWM TIMING IN RESONANT MODE
With variable frequency control, OUTA and OUTB can only be
high during the first half of the switching cycle (t A to t B ), whereas
OUTC and OUTD can only be high during the second half of
t D t E t F
Figure 40. SR1 and SR2 PWM Timing Diagram in Resonant Mode
Following is an example of how the ADP1043A can be used
in a series resonant topology and also achieve control of the
synchronous rectifiers. The V DS voltage of SR2 can be used to
PWM1 (OUTA)
Δ t 1
Δ t 2
control the SR signals. The ACSNS pin is connected to the
divided-down SR2 V DS voltage. This provides the timing
information for both synchronous rectifiers (see Figure 41).
PWM2 (OUTB)
Δ t 3
Δ t 4
C R
L R
SR2
R 1
ACSNS
I O
R 2
PWM3 (OUTC)
Δ t 5
Δ t 6
I R
SR1
C O
R L
Figure 41. Resonant Synchronous Rectifier Control Circuit
PWM4 (OUTD)
Δ t 7
Δ t 8
After the timing information is obtained, SR1 is driven by the
rising edge of the ACSNS comparator, and SR2 is driven by the
falling edge of the comparator, as shown in Figure 40. In this
t PERIOD
t PERIOD
way, it is possible to achieve synchronous rectification. Turn-on
t A
t B
t C
and turn-off delays can be programmed for the SR1 and SR2
Figure 39. OUTA, OUTB, OUTC, and OUTD PWM Timing Diagram
in Resonant Mode
signals individually.
This example is not the only way to control the SR signals. If the
user has another method to control the SR signals, this method
can be used to connect to the ACSNS input instead of the V DS
voltage of SR2.
Rev. 0 | Page 65 of 72
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