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| 型号： | ADP1043AFB100EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 35/72页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION ADP1043A 100W |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 已用 IC / 零件： | ADP1043A |
| 主要属性： | * |
| 次要属性： | * |
| 已供物品： | 板 |
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ADP1043A
DETAILED REGISTER DESCRIPTIONS
FAULT REGISTERS
Register 0x04 to Register 0x07 are latched fault registers. In these registers, flags are not reset when the fault disappears. Flags are cleared
only by a register read (provided that the fault no longer persists). Note that latched bits are clocked on a low-to-high transition only. Also
note that these register bits are cleared when read via the I 2 C interface unless the fault is still present. It is recommended that the latched
fault register be read again after the faults disappear to ensure that the register is reset.
Table 8. Register 0x00—Fault Register 1 and Register 0x04—Latched Fault Register 1 (1 = Fault, 0 = Normal Operation)
Bits
7
Name
Power supply
R/W
R
Description
1 = power supply is off. All PWM outputs are disabled. This bit
Register
Action
None
stays high until the power supply is restarted.
6
5
OrFET
PGOOD1 fault
R
R
1 = OrFET control signal at the GATE pin (Pin 16) is off.
1 = Power-Good 1 fault. At least one of the following flags has been
0x30
None
set: power supply, CS1 fast OCP, CS1 accurate OCP, CS2 accurate
OCP, UVP, local OVP, or load OVP.
4
PGOOD2 fault
R
1 = Power-Good 2 fault. At least one of the following flags has
0x2D
None
been set: power supply, OrFET, CS1 fast OCP, CS1 accurate OCP,
CS2 accurate OCP, voltage continuity, UVP, accurate OrFET disable,
ACSNS, external flag (FLAGIN), VCORE OV, VDD OV, local OVP, load
OVP, OTP, CRC fault, and EEPROM unlocked. (The user can choose to
ignore one or more flags. See Table 41 for more information.)
3
SR off
R
Sync rects are disabled. This flag is set when one of the following
None
cases is true:
SR1 and SR2 are disabled by the user.
The load current has fallen below the threshold in Register 0x3B.
A flag that was configured to disable the sync rects has been set.
0x5D
0x3B
0x08 to 0x0D
2
CS1 fast OCP
R
CS1 current is above its fast overcurrent protection limit. This is a
Programmable
1.2 V threshold on the CS1 pin. Fast OCP is a comparator.
1
0
CS1 accurate OCP
CS2 accurate OCP
R
R
CS1 current is above its accurate overcurrent protection limit.
CS2 current is above its accurate overcurrent protection limit.
0x22
0x26
Programmable
Programmable
Table 9. Register 0x01—Fault Register 2 and Register 0x05—Latched Fault Register 2 (1 = Fault, 0 = Normal Operation)
Bits
7
Name
Voltage
R/W
R
Description
Voltage differential between VS1 and VS2 pins or between VS2
Register
Action
Programmable
continuity
and VS3 pins is outside limits. Either (VS1 ? VS2) > 100 mV or
(VS2 ? VS3) > 100 mV.
6
5
UVP
Accurate OrFET
R
R
VS1 is below its undervoltage limit.
Reverse voltage across CS2 pins is above limit. This is the accurate
0x34
0x30
Programmable
Programmable
disable
OrFET reverse voltage.
4
3
VDD UV
VCORE OV
R
R
VDD is below limit.
2.5 V VCORE is above limit.
Immediate shutdown
Immediate shutdown
2
VDD OV
R
VDD is above limit. The I 2 C interface stays functional, but a PSON
0x0E
Programmable
toggle is required to restart the power supply.
1
0
Load OVP
Local OVP
R
R
VS2 or VS3 is above its overvoltage limit.
VS1 is above its overvoltage limit.
0x33
0x32
Programmable
Programmable
Table 10. Register 0x02—Fault Register 3 and Register 0x06—Latched Fault Register 3 (1 = Fault, 0 = Normal Operation)
Bits
7
6
5
4
Name
OTP
Reserved
Share bus
Constant current
R/W
R
R
R
R
Description
Temperature is above OTP limit.
Reserved.
Current share is outside regulation limit.
Power supply is operating in constant current mode (constant
Register
0x2F
0x2A
0x27
Action
Programmable
Programmable
None
current mode is enabled).
3
Reserved
R
Reserved.
2
1
0
Line impedance
Soft start filter
External flag
R
R
R
Line impedance between VS2 and VS3 is above limit.
The soft start filter is in use.
The external flag pin (FLAGIN) is set.
0x35
0x5F
None
None
Programmable
Rev. 0 | Page 35 of 72
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