参数资料
型号: ADP1043AFB100EVALZ
厂商: Analog Devices Inc
文件页数: 67/72页
文件大小: 0K
描述: BOARD EVALUATION ADP1043A 100W
标准包装: 1
主要目的: 电源管理,电源监控器/跟踪器/序列发生器
已用 IC / 零件: ADP1043A
主要属性: *
次要属性: *
已供物品:
ADP1043A
RESONANT MODE REGISTER DESCRIPTIONS
Table 111. Register 0x40—PWM Switching Frequency Setting in Resonant Mode
Bits
[7:6]
[5:0]
Name
Reserved
Switching frequency
R/W
R/W
R/W
Description
Reserved.
This register sets the switching frequency of the PWM pins and enables resonant mode. To
enable resonant mode, set these bits to 0x3F (11 1111).
Table 112. Register 0x41—OUTA Rising Edge Dead Time in Resonant Mode
Bits
[7:0]
Name
Δt 1 (rising edge dead
time of OUTA)
R/W
R/W
Description
This register sets Δt 1 , which is the delay of the rising edge of OUTA from the start of the
switching cycle, t A . Each LSB corresponds to 5 ns of resolution.
Bit 7
0
0
1
Bit 6
0
0
1
Bit 5
0
0
1
Bit 4
0
0
1
Bit 3
0
0
1
Bit 2
0
0
1
Bit 1
0
0
1
Bit 0
0
1
1
Δt 1 (ns)
0
5
1275
Table 113. Register 0x42—Lowest Switching Frequency Limit Setting (Maximum Switching Cycle in Resonant Mode)
Bits
[7:0]
Name
Lowest frequency
R/W
R/W
Description
This register contains the eight MSBs of the 12-bit value of the lowest switching frequency (maxi-
mum switching cycle) limit. This value is always used with the top four bits of Register 0x44,
which contain the four LSBs of the lowest switching frequency limit. Each LSB of the 12-bit
value corresponds to 5 ns of resolution for the switching cycle. For example, if Register 0x42
is set to 0xA0 (160 decimal) and Bits[7:4] of Register 0x44 are set to 0xF (15 decimal), the
maximum switching cycle is (160 × 16 + 15) × 5 ns = 12.875 μs, and the lowest switching
frequency limit is 1/12.875 μs = 77.7 kHz.
Table 114. Register 0x43—OUTA Fallin g Edge Dead Time in Resonant Mode
Bits
[7:0]
Name
Δt 2 (falling edge dead
time of OUTA)
R/W
R/W
Description
This register sets Δt 2 , which is the difference between the falling edge of OUTA and the mid-
point of the switching cycle, t B . Each LSB corresponds to 5 ns of resolution. When the register
value is from 0x00 to 0x7F, the falling edge of OUTA is trailing t B . When the value is from 0x80
to 0xFF, the falling edge of OUTA is leading t B .
Bit 7
0
0
0
1
1
Bit 6
0
0
1
0
1
Bit 5
0
0
1
0
1
Bit 4
0
0
1
0
1
Bit 3
0
0
1
0
1
Bit 2
0
0
1
0
1
Bit 1
0
0
1
0
1
Bit 0
0
1
1
0
1
Δt 2
0 ns
5 ns trailing
635 ns trailing
640 ns leading
5 ns leading
Table 115. Register 0x44—Lowest Switching Frequency Limit Setting (Maximum Switching Cycle in Resonant Mode)
Bits
[7:4]
Name
Lowest frequency
R/W
R/W
Description
This register contains the four LSBs of the 12-bit value of the lowest switching frequency (maxi-
mum switching cycle) limit. This value is always used with the eight bits of Register 0x42, which
contain the eight MSBs of the lowest switching frequency limit. Each LSB of the 12-bit value
corresponds to 5 ns of resolution for the switching cycle. For example, if Register 0x42 is set
to 0xA0 (160 decimal) and Bits[7:4] of Register 0x44 are set to 0xF (15 decimal), the maximum
switching cycle is (160 × 16 + 15) × 5 ns = 12.875 μs, and the lowest switching frequency limit
is 1/12.875 μs = 77.7 kHz.
[3:0]
Reserved
R/W
Reserved.
Rev. 0 | Page 67 of 72
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