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参数资料
| 型号： | ADP1043AFB100EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 55/72页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION ADP1043A 100W |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 已用 IC / 零件： | ADP1043A |
| 主要属性： | * |
| 次要属性： | * |
| 已供物品： | 板 |
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ADP1043A
Table 72. Register 0x4D—OUTD Rising Edge Timing (OUTD Pin)
Bits
[7:0]
Name
t 7
R/W
R/W
Description
This register contains the eight MSBs of the 12-bit t 7 time. This value is always used with the
top four bits of Register 0x4E, which contains the four LSBs of the t 7 time. Each LSB corresponds
to 5 ns resolution.
Table 73. Register 0x4E—OUTD Rising Edge Setting (OUTD Pin)
Bits
[7:4]
Name
t 7
R/W
R/W
Description
These bits contain the four LSBs of the 12-bit t 7 time. This value is always used with the eight
bits of Register 0x4D, which contains the eight MSBs of the t 7 time. Each LSB corresponds to
5 ns resolution.
3
Modulate enable
R/W
1 = PWM modulation acts on the t 7 edge.
0 = no PWM modulation of the t 7 edge.
2
t 7 sign
R/W
1 = negative sign. Increase of PWM modulation moves t 7 right.
0 = positive sign. Increase of PWM modulation moves t 7 left.
[1:0]
Reserved
R/W
Reserved. These bits should be set to 00 for normal operation.
Table 74. Register 0x4F—OUTD Falling Edge Timing (OUTD Pin)
Bits
[7:0]
Name
t 8
R/W
R/W
Description
This register contains the eight MSBs of the 12-bit t 8 time. This value is always used with
the top four bits of Register 0x50, which contains the four LSBs of the t 8 time. Each LSB
corresponds to 5 ns resolution.
Table 75. Register 0x50—OUTD Falling Edge Setting (OUTD Pin)
Bits
[7:4]
Name
t 8
R/W
R/W
Description
These bits contain the four LSBs of the 12-bit t 8 time. This value is always used with the eight
bits of Register 0x4F, which contains the eight MSBs of the t 8 time. Each LSB corresponds to
5 ns resolution.
3
Modulate enable
R/W
1 = PWM modulation acts on the t 8 edge.
0 = no PWM modulation of the t 8 edge.
2
t 8 sign
R/W
1 = negative sign. Increase of PWM modulation moves t 8 right.
0 = positive sign. Increase of PWM modulation moves t 8 left.
[1:0]
Reserved
R/W
Reserved. These bits should be set to 00 for normal operation.
Table 76. Register 0x51—SR1 Rising Edg e Timing (SR1 Pin)
Bits
[7:0]
Name
t 9
R/W
R/W
Description
This register contains the eight MSBs of the 12-bit t 9 time. This value is always used with
the top four bits of Register 0x52, which contains the four LSBs of the t 9 time. Each LSB
corresponds to 5 ns resolution.
Table 77. Register 0x52—SR1 Rising Edg e Setting (SR1 Pin)
Bits
[7:4]
Name
t 9
R/W
R/W
Description
These bits contain the four LSBs of the 12-bit t 9 time. This value is always used with the eight
bits of Register 0x51, which contains the eight MSBs of the t 9 time. Each LSB corresponds to
5 ns resolution.
3
Modulate enable
R/W
1 = PWM modulation acts on the t 9 edge.
0 = no PWM modulation of the t 9 edge.
2
t 9 sign
R/W
1 = negative sign. Increase of PWM modulation moves t 9 right.
0 = positive sign. Increase of PWM modulation moves t 9 left.
1
0
VS balance with SR1
and SR2
Reserved
R/W
R/W
1 = volt-second balance circuit modulates SR1 and SR2, along with OUTB and OUTD. When this
bit is set, the volt-second balance modulation is applied to the rising edge of SR1 and SR2.
Reserved. This bit should be set to 0 for normal operation.
Rev. 0 | Page 55 of 72
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