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参数资料
| 型号： | ADP1043AFB100EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 43/72页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION ADP1043A 100W |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 已用 IC / 零件： | ADP1043A |
| 主要属性： | * |
| 次要属性： | * |
| 已供物品： | 板 |
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ADP1043A
Table 36. Register 0x28—Volt-Second Balance Gain Setting
Bits
[7:2]
[1:0]
Name
Reserved
VS balance gain
setting
R/W
R/W
R/W
Description
Reserved.
These bits set the gain of the volt-second balance circuit. The gain can be changed by a factor of
64. When these bits are set to 00, it takes approximately 700 ms to achieve volt-second balance.
When these bits are set to 11, it takes approximately 10 ms to achieve volt-second balance.
Bit 1
0
0
1
1
Table 37. Register 0x29—Share Bus Bandwidth
Bit 0
0
1
0
1
Volt-Second Balance Gain
1
4
16
64
Bits
[7:5]
4
Name
Reserved
Bit stream
R/W
R/W
R/W
Description
Reserved.
1 = the current sense ADC reading is output on the SHAREo pin. This bit stream can be used for
analog current sharing.
0 = the digital share bus signal is output on the SHAREo pin. This signal can be used for digital
current sharing.
3
Current share select
R/W
1 = CS1 reading used for current share.
0 = CS2 reading used for current share.
[2:0]
Share bus bandwidth
R/W
These bits determine the amount of bandwidth dedicated to the share bus. The value 000 is
the lowest possible bandwidth, and the value 111 is the highest possible bandwidth.
Table 38. Register 0x2A—Share Bus Setting
Bits
[7:4]
[3:0]
Name
Number of bits
dropped by master
Bit difference between
master and slave
R/W
R/W
R/W
Description
These bits determine how much a master device reduces its output voltage to maintain
current sharing.
These bits determine how closely a slave tries to match the current of the master device. The
higher the setting, the larger the distance that satisfies the current sharing criteria.
Table 39. Register 0x2B—Temperature Gain Trim
Bits
[7:5]
4
Name
Reserved
Gain polarity
R/W
R/W
R/W
Description
Set these bits to 000 for normal operation.
1 = negative gain is introduced.
0 = positive gain is introduced.
[3:0]
Gain trim
R/W
This register calibrates the RTD ADC gain. It calibrates for errors in the ADC. This value allows
±12% trim to be realized.
Rev. 0 | Page 43 of 72
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