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参数资料
| 型号： | ADP1043AFB100EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 29/72页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION ADP1043A 100W |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 已用 IC / 零件： | ADP1043A |
| 主要属性： | * |
| 次要属性： | * |
| 已供物品： | 板 |
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ADP1043A
COMMUNICATION
Control of the ADP1043A is carried out via the I C interface.
I 2 C INTERFACE
2
The ADP1043A is connected to the I 2 C bus as a slave device
under the control of a master device.
I 2 C Address
The I 2 C address of the ADP1043A is set by connecting an
This indicates that a data stream follows. All slave peri-
pherals connected to the serial bus respond to the start
condition and shift in the next eight bits, consisting of a
7-bit slave address (MSB first) plus a R/W bit, which
determines the direction of the data transfer, that is,
whether data is written to or read from the slave device
(0 = write, 1 = read).
external resistor from the ADD pin to AGND. Table 5 lists the
recommended resistor values and the associated I 2 C addresses.
Eight different addresses can be used. If an incorrect resistor
value is used and the resulting I 2 C address is close to a threshold
between two addresses, a flag is set (address flag in Register 0x03,
Bit 5; see Table 11).
The recommended values in Table 5 can vary by ±2 kΩ; the
ADP1043A still reports the same address. Therefore, it is recom-
mended that 1% tolerance resistors be used on the ADD pin.
I 2 C Address 0x58 is the broadcast address, which allows multiple
parts to be written to simultaneously. By using the broadcast
address instead of a specific I 2 C address from Table 5, all
ADP1043A devices on the I 2 C bus are written to. The broadcast
address can be used for write commands only.
Table 5. Recommended Resistor Values for I 2 C Addresses
2.
3.
The peripheral whose address corresponds to the
transmitted address responds by pulling the data line low
during the low period before the ninth clock pulse, known
as the acknowledge bit, and holding it low during the high
period of this clock pulse. All other devices on the bus
remain idle while the selected device waits for data to be
read from or written to it. If the R/W bit is a 0, the master
writes to the slave device. If the R/W bit is a 1, the master
reads from the slave device.
Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal and
remain stable during the high period, because a low-to-
high transition when the clock is high may be interpreted
as a stop signal.
I 2 C Address
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
Resistor Value (kΩ)
9 (or connect the ADD pin directly to AGND)
27
45
63
81
98
116
134 (or connect the ADD pin directly to VDD)
4.
5.
If the operation is a write operation, the first data byte after
the slave address is a command byte that tells the slave
device what to expect next. It may be an instruction, such
as telling the slave device to expect a block write, or it may
be a register address that tells the slave where subsequent
data is to be written.
Because data can flow in only one direction, as defined by
the R/W bit, it is not possible to send a command to a slave
device during a read operation. Before a read operation, it
may be necessary to first perform a write operation to tell
General I 2 C Timing
The ADP1043A has a timeout feature to protect against a fault
the slave what sort of read operation to expect and/or the
address from which data is to be read.
condition on the SDA line. The I 2 C interface monitors the SDA
line and, if it stays low for time 0.65 ms < t_low < 1.3 ms, the
I 2 C interface is reset and waits for another start condition.
The I 2 C specification defines specific conditions for different
types of read and write operations. General I 2 C read and write
The general I 2 C protocol operates as follows:
6.
When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the 10 th clock pulse to assert a
stop condition. In read mode, the master device releases
the SDA line during the low period before the ninth clock
pulse, but the slave device does not pull it low. This is
known as a no acknowledge bit. The master takes the data
line low during the low period before the 10 th clock pulse,
and then high during the 10 th clock pulse to assert a stop
1.
The master initiates a data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line, SDA, while the serial clock line, SCL, remains high.
condition.
If several read or write operations must be performed in succes-
sion, the master can send a repeat start condition instead of a
stop condition to begin a new operation.
Rev. 0 | Page 29 of 72
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