参数资料
型号: ADSP-21365YSWZ-2BA
厂商: ANALOG DEVICES INC
元件分类: 数字信号处理
英文描述: 16-BIT, 55.55 MHz, OTHER DSP, PQFP144
封装: MS-026BFB-HD, LQFP-144
文件页数: 10/56页
文件大小: 2748K
代理商: ADSP-21365YSWZ-2BA
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 11. Clock Periods
Timing
Requirements
Description1
tCK
CLKIN Clock Period
tCCLK
(Processor) Core Clock Period
tPCLK
(Peripheral) Clock Period = 2 × tCCLK
tSCLK
Serial Port Clock Period = (tCCLK) × SR
tSPICLK
SPI Clock Period = (tCCLK) × SPIR
1 where:
SR = serial port-to-peripheral clock ratio (wide range, determined by SPORT
CLKDIV)
SPIR = SPI-to-peripheral clock ratio (wide range, determined by SPIBAUD
register)
DAI_Px = serial port clock
SPICLK = SPI clock
Figure 6 shows core to CLKIN ratios of 6:1, 16:1, and 32:1 with
external oscillator or crystal. Note that more ratios are possible
and can be set through software using the power management
control register (PMCTL). For more information, see the
ADSP-2136x SHARC Processor Programming Reference, the
ADSP-2136x SHARC Processor Hardware Reference and Manag
ing the Core PLL on Third-Generation SHARC Processors (EE
290).
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
DIVEN
÷1, 2, 4, 8
PLLM
DELAY
PLLICLK
XTAL
OSC
CLK_CFG [1:0]
(6:1, 16:1, 32:1)
INDIV
÷1, 2
RESET
CLKIN
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 39 on Page 45 under Test Conditions for voltage
reference levels.
Note that in the user application, the PLL multiplier value
should be selected in such a way that the VCO frequency never
exceeds 800 MHz. The VCO frequency is calculated as follows:
fVCO = 2 × PLLM × fINPUT where:
fVCO is the VCO frequency.
PLLM is the multiplier value programmed.
fINPUT is the input frequency to the PLL.
fINPUT = CLKIN when the input divider is disabled and
fINPUT = CLKIN ÷ 2 when the input divider is enabled.
Timing Requirements apply to signals that are controlled by cir
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
CCLK
(CORE CLOCK)
÷2
PCLK
(PERIPHERAL CLOCK)
CLKOUT
OR
RESETOUT
Figure 6. Core Clock and System Clock Relationship to CLKIN
Rev. B
|
Page 18 of 56
|
June 2007
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