参数资料
型号: ADSP-21365YSWZ-2BA
厂商: ANALOG DEVICES INC
元件分类: 数字信号处理
英文描述: 16-BIT, 55.55 MHz, OTHER DSP, PQFP144
封装: MS-026BFB-HD, LQFP-144
文件页数: 11/56页
文件大小: 2748K
代理商: ADSP-21365YSWZ-2BA
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Power-Up Sequencing
The timing requirements for processor startup are given in
Table 12. Power-Up Sequencing Timing Requirements (Processor Startup)
Parameter
Timing Requirements
tRSTVDD
tIVDDEVDD
tCLKVDD
1
tCLKRST
tPLLRST
RESET Low Before VDDINT/VDDEXT On
VDDINT On Before VDDEXT
CLKIN Valid After VDDINT/VDDEXT Valid
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
Min
0
–50
0
102
20
Max
+200
Unit
ns
ms
μs
Switching Characteristic
tCORERST
Core Reset Deasserted After RESET Deasserted
4096tCK + 2 tCCLK
3, 4
1 Valid V
DDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 volt rails and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of
milliseconds depending on the design of the power supply subsystem.
2 Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time.
Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3 Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
4 The 4096 cycle count depends on tSRST specification in Table 14. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097
cycles maximum.
RESET
tRSTVDD
V
DDINT
V
DDEXT
CLKIN
CLK_CFG1-0
RSTOUT
tPLLRST
tCLKRST
tCLKVDD
t
IVDDEVDD
tCORERST
Figure 7. Power-Up Sequencing
Rev. B
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Page 19 of 56
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June 2007
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