参数资料
型号: ADSP-21365YSWZ-2BA
厂商: ANALOG DEVICES INC
元件分类: 数字信号处理
英文描述: 16-BIT, 55.55 MHz, OTHER DSP, PQFP144
封装: MS-026BFB-HD, LQFP-144
文件页数: 21/56页
文件大小: 2748K
代理商: ADSP-21365YSWZ-2BA
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 23. 16-Bit Memory Read Cycle
Parameter
K and B Grade
Min
Max
Y Grade
Min
Max
Unit
Timing Requirements
tDRS
AD15–0 Data Setup Before RD High
tDRH
AD15–0 Data Hold After RD High
Switching Characteristics
tALEW
ALE Pulse Width
tADAS
1
AD15–0 Address Setup Before ALE Deasserted
tALERW
ALE Deasserted to Read Asserted
tRRH
2
Delay Between RD Rising Edge to Next Falling
Edge
tRWALE
Read Deasserted to ALE Asserted
tRDDRV
ALE Address Drive After Read High
tADAH
1
AD15–0 Address Hold After ALE Deasserted
tALEHZ1
ALE Deasserted to Address/Data15–0 in High Z
tRW
RD Pulse Width
3.3
0
2 × tPCLK – 2.0
tPCLK – 2.5
2 × tPCLK – 3.8
H + tPCLK – 1.4
F + H + 0.5
F + H + tPCLK – 2.3
tPCLK – 2.3
tPCLK
tPCLK + 3.0
D – 2.0
4.5
0
2 × tPCLK – 2.0
tPCLK – 2.5
2 × tPCLK – 3.8
H + tPCLK – 1.4
F + H + 0.5
F + H + tPCLK – 2.3
tPCLK – 2.3
tPCLK
tPCLK + 3.8
D – 2.0
ns
D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register)
× t
PCLK
H = tPCLK (if a hold cycle is specified, else H = 0)
F = 7
× t
PCLK (if FLASH_MODE is set, else F = 0)
tPCLK = (peripheral) clock period = 2
× t
CCLK
1 On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
2 This parameter is only available when in EMPP = 0 mode.
AD15-0
WR
t
DRS
t
DRH
t
ALEHZ
t
ADAH
t
ADAS
VALID ADDRESS
VALID DATA
t
ALEW
tRW
t
ALERW
t
RRH
ALE
RD
tRWALE
tRDDRV
VALID
ADDRESS
NOTE: FOR 16-BIT MEMORY READS, WHEN EMPP
0, ONLY ONE RD PULSE OCCURS BETWEEN ALE CYCLES.
WHEN EMPP = 0, MULTIPLE
RD PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,
SEE THE ADSP-2136X SHARC PROCESSOR HARDWARE REFERENCE.
Figure 19. Read Cycle for 16-Bit Memory Timing
Rev. B
|
Page 28 of 56
|
June 2007
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