参数资料
型号: ADSP-21365YSWZ-2BA
厂商: ANALOG DEVICES INC
元件分类: 数字信号处理
英文描述: 16-BIT, 55.55 MHz, OTHER DSP, PQFP144
封装: MS-026BFB-HD, LQFP-144
文件页数: 19/56页
文件大小: 2748K
代理商: ADSP-21365YSWZ-2BA
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Memory Read—Parallel Port
Use these specifications for asynchronous interfacing to memo
ries (and memory-mapped peripherals) when the ADSP-2136x
is accessing external memory space.
Table 22. 8-Bit Memory Read Cycle
Parameter
K and B Grade
Min
Max
Y Grade
Min
Max
Unit
Timing Requirements
tDRS
1
AD7–0 Data Setup Before RD High
tDRH
AD7–0 Data Hold After RD High
tDAD
1
AD15–8 Address to AD7–0 Data Valid
Switching Characteristics
tALEW
ALE Pulse Width
tADAS
2
AD15–0 Address Setup Before ALE Deasserted
tRRH
Delay Between RD Rising Edge to Next
Falling Edge
tALERW
ALE Deasserted to Read Asserted
tRWALE
Read Deasserted to ALE Asserted
tADAH
AD15–0 Address Hold After ALE Deasserted
tALEHZ
ALE Deasserted to AD7–0 Address in High Z
tRW
RD Pulse Width
tRDDRV
AD7–0 ALE Address Drive After Read High
tADRH
AD15–8 Address Hold After RD High
tDAWH
AD15–8 Address to RD High
3.3
0
D + tPCLK – 5.0
2 × tPCLK – 2.0
tPCLK – 2.5
H + tPCLK – 1.4
2 × tPCLK – 3.8
F + H + 0.5
tPCLK – 2.3
tPCLK
tPCLK + 3.0
D – 2.0
F + H + tPCLK – 2.3
H
D + tPCLK – 4.0
4.5
0
D + tPCLK – 5.0
2 × tPCLK – 2.0
tPCLK – 2.5
H + tPCLK – 1.4
2 × tPCLK – 3.8
F + H + 0.5
tPCLK – 2.3
tPCLK
tPCLK + 3.8
D – 2.0
F + H + tPCLK – 2.3
H
D + tPCLK – 4.0
ns
D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register)
× t
PCLK
H = tPCLK (if a hold cycle is specified, else H = 0)
F = 7
× t
PCLK (if FLASH_MODE is set, else F = 0)
tPCLK = (peripheral) clock period = 2
× t
CCLK
1 The timing specified here is sufficient to satisfy either t
DAD or tDRS as they are independent.
2 On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
Rev. B
|
Page 26 of 56
|
June 2007
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