参数资料
型号: ADSP-21365YSWZ-2BA
厂商: ANALOG DEVICES INC
元件分类: 数字信号处理
英文描述: 16-BIT, 55.55 MHz, OTHER DSP, PQFP144
封装: MS-026BFB-HD, LQFP-144
文件页数: 6/56页
文件大小: 2748K
代理商: ADSP-21365YSWZ-2BA
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 4. Pin Descriptions (Continued)
Pin
Type
State During and
After Reset
Function
RSTOUT/CLKOUT
RESET
TCK
TMS
TDI
TDO
TRST
EMU
VDDINT
VDDEXT
AVDD
AVSS
GND
O
I/A
I
I/S
(pu)
I/S
(pu)
O
I/A
(pu)
O (O/D)
(pu)
P
G
Output only
Input only
Input only3
Three-state with
pull-up enabled
Three-state with
pull-up enabled
Three-state4
Three-state with
pull-up enabled
Three-state with
pull-up enabled
Local Clock Out/Reset Out. Drives out the core reset signal to an external device.
CLKOUT can also be configured as a reset out pin. The functionality can be switched
between the PLL output clock and reset out by setting Bit 12 of the PMCTREG register.
The default is reset out.
Processor Reset. Resets the ADSP-2136x to a known state. Upon deassertion, there is
a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET input must be asserted
(low) at power-up.
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the processors.
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 k
Ω
internal pull-up resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
22.5 k
Ω internal pull-up resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the ADSP-2136x. TRST has a
22.5 k
Ω internal pull-up resistor.
Emulation Status. Must be connected to the processor’s JTAG emulators target board
connector only. EMU has a 22.5 k
Ω internal pull-up resistor.
Core Power Supply. Nominally +1.2 V dc for the K, B grade models, and 1.0 V dc for
the Y grade models, and supplies the processor’s core (13 pins).
I/O Power Supply. Nominally +3.3 V dc (6 pins).
Analog Power Supply. Nominally +1.2 V dc for the K, B grade models, and 1.0 V dc for
the Y grade models, and supplies the processor’s internal PLL (clock generator). This
pin has the same specifications as VDDINT, except that added filtering circuitry is
Analog Power Supply Return.
Power Supply Return. (54 pins)
1 RD, WR, and ALE are three-stated (and not driven) only when RESET is active.
2 Output only is a three-state driver with its output path always enabled.
3 Input only is a three-state driver with both output path and pull-up disabled.
4 Three-state is a three-state driver with pull-up disabled.
Rev. B
|
Page 14 of 56
|
June 2007
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