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参数资料
| 型号： | ADSP-21365YSWZ-2BA |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 16-BIT, 55.55 MHz, OTHER DSP, PQFP144 |
| 封装： | MS-026BFB-HD, LQFP-144 |
| 文件页数： | 56/56页 |
| 文件大小： | 2748K |
| 代理商： | ADSP-21365YSWZ-2BA |
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
digital buses, such as the IEEE 1394 standard. Only legitimate
entertainment content delivered to a source device via another
approved copy protection system (such as the DVD content
scrambling system) will be protected by this copy protection
system. This feature is available on the ADSP-21362 and
ADSP-21365 processors only. Licensing through DTLA is
required for these products. Visit www.dtcp.com for more
information.
Pulse-Width Modulation
The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
generate either center-aligned or edge-aligned PWM wave
forms. In addition, it can generate complementary signals on
two outputs in paired mode or independent signals in non-
paired mode (applicable to a single group of four PWM
waveforms).
The entire PWM module has four groups of four PWM outputs
each. Therefore, this module generates 16 PWM outputs in
total. Each PWM group produces two pairs of PWM signals on
the four PWM outputs.
The PWM generator is capable of operating in two distinct
modes while generating center-aligned PWM waveforms: single
update mode or double update mode. In single update mode the
duty cycle values are programmable only once per PWM period.
This results in PWM patterns that are symmetrical about the
midpoint of the PWM period. In double update mode, a second
updating of the PWM registers is implemented at the midpoint
of the PWM period. In this mode, it is possible to produce
asymmetrical PWM patterns that produce lower harmonic dis
tortion in three-phase PWM inverters.
Timers
The ADSP-2136x has a total of four timers: a core timer that can
generate periodic software interrupts and three general-purpose
timers that can generate periodic interrupts and be indepen
dently set to operate in one of three modes:
Pulse waveform generation mode
Pulse width count/capture mode
External event watchdog mode
The core timer can be configured to use FLAG3 as a timer
expired signal, and each general-purpose timer has one bidirec
tional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse width register. A sin
gle control and status register enables or disables all three
general-purpose timers independently.
ROM-Based Security
The ADSP-2136x has a ROM security feature that provides
hardware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the processor does not boot-load any
external code, executing exclusively from internal SRAM/ROM.
Additionally, the processor is not freely accessible via the JTAG
port. Instead, a unique 64-bit key, which must be scanned in
through the JTAG or test access port will be assigned to each
customer. The device will ignore a wrong key. Emulation fea
tures and external boot modes are only available after the
correct key is scanned.
Program Booting
The internal memory of the ADSP-2136x boots at system
power-up from an 8-bit EPROM via the parallel port, an SPI
master, an SPI slave, or an internal boot. Booting is determined
by the boot configuration (BOOTCFG1–0) pins (see Table 7 on
Page 15). Selection of the boot source is controlled via the SPI as
either a master or slave device, or it can immediately begin exe
cuting from ROM.
Phase-Locked Loop
The processors use an on-chip phase-locked loop (PLL) to gen
erate the internal clock for the core. On power up, the
CLKCFG1–0 pins are used to select ratios of 32:1, 16:1, and 6:1
(see Table 8 on Page 15). After booting, numerous other ratios
can be selected via software control.
The ratios are made up of software configurable numerator val
ues from 1 to 64 and software configurable divisor values of 1, 2,
4, and 8.
Power Supplies
The ADSP-2136x has a separate power supply connection for
the internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS)
power supplies. The internal and analog supplies must meet the
1.2 V requirement for K, B, and Y grade models, and the 1.0 V
requirement for Y models. (For information on the temperature
ranges offered for this product, see Operating Conditions on
on Page 53. The external supply must meet the 3.3 V require
ment. All external supply pins must be connected to the same
power supply.
Note that the analog supply pin (AVDD) powers the processor’s
internal clock generator PLL. To produce a stable clock, it is rec
ommended that PCB designs use an external filter circuit for the
AVDD pin. Place the filter components as close as possible to the
mended ferrite chip is the muRata BLM18AG102SN1D). To
reduce noise coupling, the PCB should use a parallel pair of
power and ground planes for VDDINT and GND. Use wide traces
to connect the bypass capacitors to the analog power (AVDD) and
ground (AVSS) pins. Note that the AVDD and AVSS pins specified in
Figure 4 are inputs to the processor and not the analog ground
plane on the board—the AVSS pin should connect directly to dig
ital ground (GND) at the chip.
Target Board JTAG Emulator Connector
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the processor to moni
tor and control the target board processor during emulation.
Analog Devices’ DSP Tools product line of JTAG emulators
provides emulation at full processor speed, allowing inspection
Rev. B
|
Page 9 of 56
|
June 2007
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-21365YSWZ-2CA | 功能描述:IC DSP 32BIT 200MHZ EPAD 144LQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21366 | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
| ADSP-21366BBC-1AA | 功能描述:数字信号处理器和控制器 - DSP, DSC 333 MHz SHARC with on chipRom RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| ADSP-21366BBCZ-1AA | 功能描述:数字信号处理器和控制器 - DSP, DSC 333 MHz SHARC with on chipRom RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| ADSP-21366BSWZ-1AA | 功能描述:IC DSP 32BIT 333MHZ EPAD 144LQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
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