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参数资料
| 型号： | AT76C551 |
| 厂商： | ATMEL CORP |
| 元件分类： | 通信及网络 |
| 英文描述： | Single Chip Bluetooth Controller(单芯片蓝牙技术控制器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP176 |
| 封装： | LQFP-176 |
| 文件页数： | 14/51页 |
| 文件大小： | 845K |
| 代理商： | AT76C551 |
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AT76C551
14
Register Description
Memory Controller Register Set
The Memory Controller Register Set can be configured to
cooperate with various types of external Flash and SRAM
memories. The configuration parameters are held by Mem-
ory Configuration Registers (MCR) which are mapped into
AMBA memory space. After AT76C551 resets, MCR
default values guarantee correct operation of external
Flash or SRAM memories connected to AT76C551.
AT76C551 firmware adjusts Memory Configuration Regis-
ters in order to achieve Flash and SRAM safe operation
with minimum wait states.
In the reset configuration the external Flash can be found
at the bottom of the address map. If the bit 0 of the remap
register is set high, then the Memory Controller switches to
the normal memory map in where there is internal SRAM.
Table
SRAM Configuration Register (MCR0)
Addr: E00000 hex
R/W
8-bits
Note:
Default Value: 77 hex
Table
Flash Memory Configuration Register (MCR1)
Addr: E00004 hex
R/W
8-bits
Note:
Default Value: 07 hex
Table
Flash and Internal SRAM remap Register (MCR2)
Addr: E00008 hex
R/W
8-bits
Note:
Default Value: 00 hex
PCMCIA Configuration Registers
The PCMCIA configuration registers are required by the
PCMCIA standard. These registers are mapped into PCM-
CIA attribute memory space to allow the host to configure
basic parameters of the PCMCIA device. They are accessi-
ble by the host but they are not accessible by ARM core.
Table
Configuration Option Register (COR)
PCMCIA Addr: 0800 hex
R/W
8-bits
Note:
Default Value: 00 hex
Table
Configuration & Status Register (CSR)
PCMCIA Addr: 0802 hex
R/W
8-bits
Note:
Default Value: 00 hex
System Interface Registers (SIR)
The System Interface Registers (SIR) lie in the PCMCIA
interface unit. They are mapped into PCMCIA I/O space,
i.e. they are directly accessible by the host but they are not
directly accessible by the ARM core. They allow the host to
configure and communicate with AT76C551 through host
Bit 7
Bits
6
…
4
Bit 3
Bits
2
…
0
Reserved
Number (0 - 7) of wait states
during SRAM write cycles
Reserved
Number (0 - 7) of wait states
during SRAM read cycles
SWW[2:0]
SWR[2:0]
Bits
7
…
3
Bits
2
…
0
Reserved
FWR[2:0]
Number (0 - 7) of wait states
during FLASH memory read
cycles
Bits
7
…
1
Bits 0
Reserved
REMAP
Remap enable
Bit 7
SRES
System Reset
By setting this bit, the device
is reset in a way equivalent to
PCMCIA hardware reset
signal activation. Note that this
bit is not automatically cleared
after set
Logic 1: Level mode interrupt.
Logic 0: Pulse mode interrupt
Configuration Index: This field
is written with the index
number of the entry in the
card
’
s configuration table
which the host selects. When
all the field bits are zero, the
device is in memory only
mode.
Bit 6
IEVREQ
Bits
5
…
0
CFX[5:0]
Bits
7
…
6
Bit 5
Reserved
IOIS8
Logic 1: The host is only
capable of 8-bit I/O accesses.
Logic 0: The host is capable of
8-bit and 16-bit I/O accesses
Reserved
Bits
4
…
0
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