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参数资料
| 型号： | AT76C551 |
| 厂商： | ATMEL CORP |
| 元件分类： | 通信及网络 |
| 英文描述： | Single Chip Bluetooth Controller(单芯片蓝牙技术控制器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP176 |
| 封装： | LQFP-176 |
| 文件页数： | 24/51页 |
| 文件大小： | 845K |
| 代理商： | AT76C551 |
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AT76C551
24
Table
CLKPhaseCorrelCorrect
Addr: 60002C hex
R/W
32-bits
Note:
Default Value: 00000000 hex
Table
CLKPhaseLimit
Addr: 600030 hex
R/W
32-bits
Note:
Default Value: 00000000 hex
Table
CLKPhaseWhenCorrel
Addr: 600034 hex
R/W
32-bits
Note:
Default Value: 00000000 hex
Table
CLKCtrl
Addr: 600038 hex
R/W
32-bits
Note:
Default Value: 00000000 hex
Table
CmpTimer_RxTxStart
Addr: 60003C hex
R/W
32-bits
Note:
Default Value: 00000000 hex
Table
CmpTimer_GenPurpose
Addr: 600040 hex
R/W
32-bits
Note:
Default Value: 00000000 hex
Bits
31...15
Bits
14
…
0
Reserved
CLKPhase_
Correl_
Correct[14:0]
Provides slave
’
s HW with
the proper native clock
phase value just after
correlator trigger. At this
moment slave
’
s HW
automatically adjusts
CLKN with CLKN of
corresponding master.
Bits
31...15
Bits
14
…
0
Reserved
CLKPhase_
Limit[14:0]
Sets native clock phase
maximum value in system
clock cycles. Effectively
sets half-slot duration in
system clock cycles.
Bits
31...15
Bits
14
…
0
Reserved
CLKPhase_
When_
Correl[14:0]
Samples and holds native
clock phase at correlator
trigger. Thus enables
slave-to-master clock drift
estimation
Bits
31
…
4
Reserved
Bit 3
cmpCLKN0_
invert
0: Native clock bit 0 is not
inverted for timer
comparisons.
1: Native clock bit 0 is
inverted for timer
comparisons.
Bit 3 value is
“
don
’
t care
”
if
bit 0 of the register is reset.
Set by firmware to force
native clock phase
adjustment, i.e. set native
clock phase equal to
CLKPhaseCorrelCorrect
register contents.
Auto-clear.
0: Native clock phase is not
auto-adjusted.
1: Native clock phase is
auto-adjusted, i.e. set equal
to
CLKPhaseCorrelCorrect
register contents just after
each correlator trigger.
0: Compare timer event is
generated when compare
timer bits 14-0 are equal to
native clock phase.
1: Compare timer event is
generated when compare
timer bits 14-0 are equal to
native clock phase AND
compare timer bit 15 is equal
to native clock bit 0 (possibly
inverted).
Bit 2
ForcePhase_
Adjust
Bit 1
AutoPhaseAdjust
Bit 0
cmpCLKN0_
enable
Bits
15
…
0
CmpTimer_
RxTxStart[15:0]
Sets compare timer for
packet RX or TX
procedure start.
Bits
15
…
0
CmpTimer_
GenPurpose[15:0]
Sets general
purpose compare
timer
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