AT76C551
47
Timer Device Registers
AT76C551 incorporates two (2) identical and completely
independent system timer devices, Timer Device 1 and
Timer Device 2.
Each Timer Device is implemented as a 32-bit down
counter which advances at a programmable rate driven by
a prescale circuit. The counter is loaded with a programma-
ble 32-bit value (preload) when the Timer Device is
enabled. When the counter reaches zero an interrupt to the
ARM core is generated. Timer Device behavior after the
counter reaches zero depends on the selected operating
mode. In one-shot mode the counter stops and no interrupt
is generated to the ARM until the Timer Device is reen-
abled. In periodic mode the counter is reloaded with the
preload value and countdown is continued, effectively gen-
erating a periodic interrupt to the ARM core.
AT76C551 firmware can program and control each Timer
Device via registers mapped into AMBA memory space
and thus accessible by the ARM core. The following regis-
ters program and control each Timer Device.
Table
Timer Device Registers
Table
Timer Preload Low Register
R/W
16-bits
Table
Timer Preload High Register
R/W
16-bits
Table
Timer Value Low Register
R
16-bits
Table
Timer Value High Register
R
16-bits
Table
Timer Prescale Register
R/W
16-bits
Note:
The Timer Prescale Register must contain a non-zero
value for proper Timer Device operation.
Table
Timer Control Register
R/W 16-bits
Table
Timer Interrupt Clear Register
W
16-bits
Register Name
AMBA address
for Timer Device
1
F200000h
AMBA address
for Timer Device
2
F200020h
Timer Preload Low
Register
Timer Preload High
Register
Timer Value Low
Register
Timer Value High
Register
Timer Prescale
Register
Timer Control
Register
Timer Interrupt
Clear Register
F200004h
F200024h
F200008h
F200028h
F20000Ch
F20002Ch
F200010h
F200030h
F200014h
F200034h
F200018h
F200038h
Timer Preload Low Register and Timer Preload High
Register contain the 32-bit preload value.
Timer Value Low Register and Timer Value High Register
reflect the 32-bit counter current value. Note that full 32-
bit counter value can be acquired by reading both Timer
Value Low Register and Timer Value High Register, but
result consistency cannot be guaranteed by the Timer
Device and must be ensured by software means.
Timer Prescale Register sets the divisor for the prescale
circuit. If Timer Prescale Register contains p and PAI
clock frequency is f (MHz) then countdown rate for the
Timer Device counter will be r = f/p
Bits
15
…
2
Reserved
Return 0 when read
Bit 1
Enable
Logic 1: The counter is
allowed to run.
Logic 0: The counter is
stopped. The Timer Device
may be configured via Timer
Preload Low Register, Timer
Preload High Register and
Timer Prescale Register.
Logic 1: Periodic mode
operation is selected.
Logic 0: One-shot mode
operation is selected.
Bit 0
Periodic
Writing Timer Interrupt Clear Register with any value
clears an interrupt generated by the Timer Device.