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参数资料
| 型号： | AT76C551 |
| 厂商： | ATMEL CORP |
| 元件分类： | 通信及网络 |
| 英文描述： | Single Chip Bluetooth Controller(单芯片蓝牙技术控制器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP176 |
| 封装： | LQFP-176 |
| 文件页数： | 31/51页 |
| 文件大小： | 845K |
| 代理商： | AT76C551 |
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AT76C551
31
Voice CODEC Register Set
The Voice CODEC has four modes: CVSD, a-law, u-law
and passthrough where data is transferred out through the
digital interface. The module has independent receive and
trasmit paths- each having a dedicated 32-byte FIFO.
Table
Voice CODEC Analog Control (VC_CTRL)
Addr: 500000 hex
R/W
Bits
15...13
13 bits
Note:
Default Value: 0000 hex
Before conversions can take place the ADC and the DAC
must be powered up. The ADC requires 10 us power-up
time while the DAC 20 us power-up time. During this time,
the coding modules must not be enabled. After powering
up, the ADC/DAC conversion rate and the required coding
mode can be programmed.
Table
Voice CODEC Digital Interface Control
(VCDI_MODE)
Addr: 500004 hex
R/W
16-bits
Note:
Default Value: 0000 hex
The digital interface is able to operate either as a master or
a slave. When operating as a master, a 6.144 MHz clock is
used, while in slave mode, the clock available at the
ABCLK_IN pin is used to drive the digital interface.
Table
Voice CODEC Interrupt Control Status
(VC_INT_CTRL_STATUS)
Addr: 500008 hex
R/W
16-bits
Note:
Default Value: 0000 hex
Reserved
Bit 12
Rate
Rate
1= 64 kHz sampling rate
0= 8 kHz sampling rate
type of AD conversion
00=reserved
01=reserved
10=reserved
11= conversion initiated
by 64/8 kHz clock
Start conversion
Enables ADC converter
Enables DAC converter
Enables digital interface
Enables a-law decoder
Enables u-law decoder
Enables CVSD decoder
Enables a-law encoder
Enables u-law encoder
Enables CVSD encoder
Bits
11...10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADC_TC[1:0]
ADC_SC
ADC_EN
DAC_EN
DIG_INT
AL_DEC
UL_DEC
CV_DEC
AL_ENC
UL_ENC
CV_ENC
Bits
15...6
Bit 5
Reserved
ENA
Enables serial
transmission
1= enabled
0= not enabled
Output Sample Format
1 = 16 bits
0 = 8 bits
Audio Clock Direction
1= Digital interface is
slave
0= Digital interface is
master
Reserved
Master Audio Clock
Divider Control
00= aclk is driven by
mclock
01=aclk =mclock / 2
10=aclk = mclock / 4
11=aclk = mclock / 8
Bit 4
OSF
Bit 3
DIR
Bit 2
Bits
1
…
0
M_CDC[1:0]
Bits
15...4
Bit 3
Reserved
EN_RC_I
Enable Voice CODEC
Transmit FIFO interrupt
Enable Voice CODEC
Receive FIFO interrupt
Transmit FIFO interrupt
status
Receive FIFO interrupt
status
Bit 2
EN_TR_I
Bit 1
VCRC_S
Bit 0
VCTR_S
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