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参数资料
| 型号： | AT76C551 |
| 厂商： | ATMEL CORP |
| 元件分类： | 通信及网络 |
| 英文描述： | Single Chip Bluetooth Controller(单芯片蓝牙技术控制器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP176 |
| 封装： | LQFP-176 |
| 文件页数： | 39/51页 |
| 文件大小： | 845K |
| 代理商： | AT76C551 |
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AT76C551
39
Once this bit is set the USB H/W passes packets to and
from the Host.
Table
ENDPPGPG : Endpoint Ping-Pong Enable Register
addr 50003C4h
R
8-bits
Table
Endpoint Control Registers
Addr: see below8-bits
Note:
Default: 00h
Table
Endpoint Control Registers Address
Table
Endpoint Control and Status Register
Addr: see below
8-bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Enable Endpoint 6 Ping-Pong
Enable Endpoint 5 Ping-Pong
Enable Endpoint 4 Ping-Pong
Enable Endpoint 3 Ping-Pong
Enable Endpoint 2 Ping-Pong
Enable Endpoint 1 Ping-Pong
Enable Endpoint 0 Ping-Pong
PG_EP6_EN
PG_EP5_EN
PG_EP4_EN
PG_EP3_EN
PG_EP2_EN
PG_EP1_EN
PG_EP0_EN
Bit 7
R
EPEDS
Endpoint Enable/Disable
( 0 = Disable Endpoint, 1 =
Enable Endpoint)
Reserved
Reserved and set to 0
Bit 6
Bits
5
…
4
Bit 3
W
Bit 2
R
DTGLE
Data Toggle. Identifies DATA0 or
DATA1 packets
EPDIR
Endpoint Direction.
Only applicable for non-Control
Endpoints ( 0 =Out, 1 =In).
Endpoint Type.
These bits represent the type of
the Endpoint as follows:
Bit1 Bit0 Type
0 0 Control
0 1 Isochronous
1 0 Bulk
1 1 Interrupt
Bits 1..0
R
EPTYPE
Address
D0003BCh
D0003B8h
D0003B4h
D0003B0h
D0003ACh
D0003A8h
D0003A4h
Register
ENDP0_CNTR Endpoint 0
ENDP1_CNTR Endpoint 1
ENDP2_CNTR Endpoint 2
ENDP3_CNTR Endpoint 3
ENDP4_CNTR Endpoint 4
ENDP5_CNTR Endpoint 5
ENDP6_CNTR Endpoint 6
Bit 7
R
Control Direction
Set by the processor to
indicate to the USB H/W the
direction of a control transfer.
0 = control write. No data
stage
1 = control read
This bit is used by Control
Endpoints only.
Indicate that the processor
has placed the last data
packet in FIFO0, or that the
processor has processed the
last data packet it expects
from the Host.
Set by the processor to
indicate a stalled Endpoint.
The H/W will send a STALL
handshake as a response to
the next IN or OUT token.
Indicates that the processor
has loaded the FIFO with a
packet of data. This bit is
cleared by H/W after the USB
Host acknowledges the
packet. For ISO Endpoints,
this bit is cleared
unconditionally after the data
is sent.
The USB H/W sets this bit
after a STALL is sent to the
Host.
Indicates End of data stage for
the Control Endpoint only.
The USB H/W sets this bit
when it receives a valid setup
packet from the Host. This bit
is used by Control Endpoints
only.
Bit 6
R
Data End
Bit 5
R
Force Stall
Bit 5
R/C
TX Packet
Ready
Bit 3
W
Stall Snd
Bit 2
W
RX SETUP
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